Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 64c8490de74899a82571b1f380d13a31c1f07574 / plat / xilinx / versal / include
  1. 2f4cc71 xilinx: versal: Wire silicon default setup by Siva Durga Prasad Paladugu · 6 years ago
  2. 5aa76f9 versal: Increase OCM memory size for DEBUG builds by Venkatesh Yadav Abbarapu · 5 years ago
  3. 41dd096 plat: xilinx: versal: Dont set IOU switch clock by Siva Durga Prasad Paladugu · 5 years ago
  4. 10161e5 arm64: versal: Adjust cpu clock for versal virtual by Siva Durga Prasad Paladugu · 6 years ago
  5. 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · 6 years ago
  6. 044001d xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API by Tejas Patel · 6 years ago
  7. fe0e10a xilinx: versal: Add support for suspend related APIs by Tejas Patel · 5 years ago
  8. 354fe57 xilinx: Add support to send PM API to PMC using IPI for versal by Tejas Patel · 6 years ago
  9. 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · 6 years ago
  10. 6940996 plat: xilinx: versal: Move versal_private.h to include directory by Tejas Patel · 6 years ago
  11. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  12. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · 6 years ago