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git01.mediatek.com / filogic / atf / 601729ece590b983a1a30ca720a2de61c05d627a / fdts / stm32mp157a-avenger96.dts
  1. e658cfe feat(stm32mp1-fdts): remove PLL1 settings by Gabriel Fernandez · 1 year, 10 months ago
  2. df4be52 feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1 by Gabriel Fernandez · 2 years, 3 months ago
  3. 7a4308f feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation by Lionel Debieve · 2 years, 9 months ago
  4. e37d905 refactor(stm32mp15-fdts): remove unused secure-status properties by Yann Gautier · 2 years, 8 months ago
  5. f55efba refactor(stm32mp15-fdts): remove RCC secure-status by Yann Gautier · 2 years, 8 months ago
  6. 9d3c53c fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver by Ahmad Fatoum · 2 years, 6 months ago
  7. 4ede20a fdts: stm32mp1: realign device tree with kernel by Yann Gautier · 4 years, 2 months ago
  8. dd445ab fdts: stm32mp1: move FDCAN to PLL4_R by Antonio Borneo · 5 years ago
  9. 02a66d6 stm32mp1: Add Avenger96 board support by Manivannan Sadhasivam · 6 years ago