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filogic
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atf
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5f939a90655c1593a9644f0a1b55ec0bbcbec372
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include
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arch
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aarch32
/
el3_common_macros.S
677ed8a
refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
by Boyan Karatotev
· 1 year, 9 months ago
11b9b49
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
by Arvind Ram Prakash
· 2 years ago
0824b45
feat(bl2): add support to separate no-loadable sections
by Jiafei Pan
· 2 years, 9 months ago
b0d69e8
fix(pie): invalidate data cache in the entire image range if PIE is enabled
by Zelalem Aweke
· 3 years, 1 month ago
8ce3394
feat(trf): initialize trap settings of trace filter control registers access
by Manish V Badarkhe
· 3 years, 4 months ago
f7ee064
feat(sys_reg_trace): initialize trap settings of trace system registers access
by Manish V Badarkhe
· 3 years, 4 months ago
514e59c
Add PIE support for AARCH32
by Yann Gautier
· 4 years, 1 month ago
e57bce8
Avoid the use of linker *_SIZE__ macros
by Yann Gautier
· 4 years, 3 months ago
f3a4c54
Add support for FEAT_MTPMU for Armv8.6
by Javier Almansa Sobrino
· 4 years ago
c241b57
el3_entrypoint_common: avoid overwriting arg3
by Yann Gautier
· 4 years, 10 months ago
d2f21b8
Add missing support for BL2_AT_EL3 in XIP memory
by Lionel Debieve
· 5 years ago
9074dea
AArch32: Disable Secure Cycle Counter
by Alexei Fedorov
· 5 years ago
457c64e
aarch32: Allow compiling with soft-float toolchain
by Manish Pandey
· 6 years ago
404184d
Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd
by Antonio Niño Díaz
· 6 years ago
078e66f
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
by Usama Arif
· 6 years ago
3fbd3f5
Disable processor Cycle Counting in Secure state
by Antonio Nino Diaz
· 6 years ago
8d1ade6
Reorganize architecture-dependent header files
by Antonio Nino Diaz
· 6 years ago
[Renamed from include/common/aarch32/el3_common_macros.S]
0f3a004
Merge pull request #1731 from miyatsu/doc-fix-20181225
by Antonio Niño Díaz
· 6 years ago