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git01.mediatek.com / filogic / atf / 5e79cfe49420aadc44e07e53a95df642b083e64b / plat / renesas / rcar / platform.mk
  1. 50a4d1a Remove unneeded include paths in PLAT_INCLUDES by Antonio Nino Diaz · Fri Feb 01 12:22:22 2019 +0000
  2. e3d1026 Revert "rcar_gen3: plat: Enable programmable CPU reset address" by Marek Vasut · Tue Jan 29 06:06:08 2019 +0100
  3. 4bc543c rcar_gen3: drivers: pwrc: Switch to common delay implementation by Marek Vasut · Fri Dec 28 20:15:33 2018 +0100
  4. 1778b41 rcar_gen3: drivers: delay: Rewrite from assembler to C by Marek Vasut · Wed Dec 26 15:57:08 2018 +0100
  5. 38ec9e5 rcar_gen3: drivers: cpld: Move rcar_cpld_reset_cpu() into header by Marek Vasut · Fri Dec 28 11:26:03 2018 +0100
  6. 83f4b84 rcar_gen3: plat: Enable programmable CPU reset address by Marek Vasut · Mon Dec 31 15:57:11 2018 +0100
  7. 1bef575 rcar_gen3: plat: Disable SVE by Marek Vasut · Fri Dec 28 20:38:09 2018 +0100
  8. 7043fce rcar_gen3: plat: Add missing dependency to rcar_srecord by Marek Vasut · Mon Dec 31 19:47:37 2018 +0100
  9. 93c85fc plat: rcar: Pass DTB with DRAM layout from BL2 to next stages by Marek Vasut · Tue Oct 02 20:45:18 2018 +0200
  10. 87c0405 rcar-gen3: control RPC hyper-flash access by Jorge Ramirez-Ortiz · Mon Nov 19 19:26:56 2018 +0100
  11. 47503d2 rcar_gen3: drivers: staging by Jorge Ramirez-Ortiz · Sun Sep 23 09:36:52 2018 +0200
  12. bf084dc rcar-gen3: initial commit for the rcar-gen3 boards by Jorge Ramirez-Ortiz · Sun Sep 23 09:36:13 2018 +0200