Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 5dd10ad908c23af65c4d6c41f0f00877d06488dd / plat / nvidia / tegra / soc / t186 / plat_secondary.c
  1. 17ad11a Tegra186: system resume from TZSRAM memory by Varun Wadekar · Fri Nov 09 09:08:16 2018 -0800
  2. f3d9b84 Tegra186: disable PROGRAMMABLE_RESET_ADDRESS by Varun Wadekar · Thu Aug 09 15:11:23 2018 -0700
  3. 186485e Tegra: rename secure scratch register macros by Steven Kao · Mon Oct 23 18:22:09 2017 +0800
  4. 8304fc8 Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1 by Varun Wadekar · Wed Oct 25 11:52:07 2017 -0700
  5. 5a4ce00 Tegra186: fix defects flagged by MISRA scan by Anthony Zhou · Wed Jun 28 16:49:16 2017 +0800
  6. faad346 Tegra186: secondary: fix MISRA defects by Anthony Zhou · Tue Mar 21 15:50:09 2017 +0800
  7. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  8. 4b32e62 libc: Fix all includes in codebase by Antonio Nino Diaz · Thu Aug 16 16:52:57 2018 +0100
  9. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  10. d007f76 Tegra186: Update API for reset vector ARI by Krishna Sitaraman · Fri Sep 02 16:53:04 2016 -0700
  11. 93bed2a Tegra186: save/restore BL31 context to/from TZDRAM by Varun Wadekar · Fri Mar 18 13:07:33 2016 -0700
  12. abd153c Tegra186: power on/off secondary CPUs by Varun Wadekar · Mon Sep 14 09:31:39 2015 +0530
  13. 921b906 Tegra186: platform support for Tegra "T186" SoC by Varun Wadekar · Tue Aug 25 17:03:14 2015 +0530