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git01.mediatek.com / filogic / atf / 5aa329b01740c2e7f78e39eb3fc24964f36b3012 / drivers / st / ddr / stm32mp1_ram.c
  1. a205a5c feat(st): use newly introduced clock framework by Yann Gautier · Mon Aug 30 15:06:54 2021 +0200
  2. 2d5690c plat/stm32: Implement fdt_read_uint32_default() as a wrapper by Andre Przywara · Thu Mar 26 11:50:33 2020 +0000
  3. cc99f3f plat/stm32: Use generic fdt_read_uint32_array() implementation by Andre Przywara · Thu Mar 26 12:51:21 2020 +0000
  4. a55169b stm32mp1: dynamically map DDR later and non-cacheable during its test by Yann Gautier · Fri Jan 10 18:18:59 2020 +0100
  5. e4a3c35 stm32mp1: update clock driver by Yann Gautier · Thu Feb 14 10:53:33 2019 +0100
  6. 3d78a2e stm32mp1: use functions to retrieve some peripheral addresses by Yann Gautier · Thu Feb 14 11:01:20 2019 +0100
  7. b5d2ed4 stm32mp1: remove some dependencies on clocks and reset in drivers by Yann Gautier · Thu Feb 14 11:13:50 2019 +0100
  8. a2e2a30 stm32mp1: make functions and macros more common by Yann Gautier · Thu Feb 14 11:13:39 2019 +0100
  9. 1a3fc9f drivers: st: update drivers code by Yann Gautier · Thu Jan 17 14:35:22 2019 +0100
  10. 7b7e4bf stm32mp1: update device tree files by Yann Gautier · Thu Jan 17 19:16:03 2019 +0100
  11. 57e282b stm32mp1: do not include platform header files directly in drivers by Yann Gautier · Mon Jan 07 11:17:24 2019 +0100
  12. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  13. caf575b stm32mp1: Add DDR support and its security with TZC400 by Yann Gautier · Tue Jul 24 17:18:19 2018 +0200