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git01.mediatek.com / filogic / atf / 5a0f9da439e834c816acd73e87b54164847f5a44 / plat / nvidia / tegra / common / aarch64
  1. c9f2953 Tegra: common: fixup the bl31 code size to be copied at reset by anzhou · Tue Aug 04 22:05:19 2020 +0800
  2. 1b3196f Tegra: remove unused cortex_a53.h by Varun Wadekar · Mon Nov 18 11:55:02 2019 -0800
  3. de947b7 Tegra: remove "platform_get_core_pos" function by Varun Wadekar · Wed Oct 16 10:43:33 2019 -0700
  4. ad2d5f3 Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler by Varun Wadekar · Tue Nov 27 15:47:26 2018 -0800
  5. 7f8d848 Tegra: aarch64: calculate core position from one place by Kalyani Chidambaram · Wed Oct 03 17:00:17 2018 -0700
  6. c9bd0aa Tegra: disable CPUACTLR access from lower exception levels by Varun Wadekar · Thu Jun 07 11:21:02 2018 -0700
  7. 09a22e7 tegra: add support for multi console interface by Ambroise Vincent · Wed May 29 14:04:16 2019 +0100
  8. fa99b22 Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position by Varun Wadekar · Wed Aug 23 16:02:06 2017 -0700
  9. 21c4272 Tegra: remove duplicate code from CPU's power on path by Varun Wadekar · Tue Aug 15 15:38:01 2017 -0700
  10. d417cea Tegra: read-modify-write ACTLR_ELx registers by Steven Kao · Wed Jun 14 14:02:23 2017 +0800
  11. 6dc0d76 Tegra210: skip the BTB invalidate workaround for B01 SKUs by Harvey Hsieh · Mon Apr 24 19:35:51 2017 +0800
  12. fbdfce1 Tegra: support to set the L2 ECC and Parity enable bit by Harvey Hsieh · Wed Nov 23 19:13:08 2016 +0800
  13. 1eb64a1 Add plat_crash_console_flush to platforms without it by Antonio Nino Diaz · Wed Oct 17 15:29:34 2018 +0100
  14. 91b11c3 Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR* by Eleanor Bonnici · Thu Aug 10 14:46:26 2017 +0100
  15. b4c75e9 Add new alignment parameter to func assembler macro by Julius Werner · Tue Aug 01 15:16:36 2017 -0700
  16. e363146 Fix order of remaining platform #includes by Isla Mitchell · Fri Jul 14 10:46:32 2017 +0100
  17. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  18. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  19. 4e6ae18 Tegra: no need to re-init the same console by Varun Wadekar · Tue Apr 04 13:40:12 2017 -0700
  20. 2bb9f47 Tegra: replace ASM signed tests with unsigned by Douglas Raillard · Mon Mar 20 10:38:29 2017 +0000
  21. 69ce101 Tegra: enable ECC/Parity protection for Cortex-A57 CPUs by Varun Wadekar · Thu May 12 13:43:33 2016 -0700
  22. 25e658e Tegra: include platform_def.h to access UART macros by Varun Wadekar · Tue Apr 26 11:38:38 2016 -0700
  23. 1ec441e Tegra: relocate code to BL31_BASE during cold boot by Varun Wadekar · Thu Mar 24 15:34:24 2016 -0700
  24. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · Thu Oct 29 10:37:28 2015 +0530
  25. 39f87d1 Tegra: use ClusterId for calculating core position by Varun Wadekar · Tue Sep 22 13:45:07 2015 +0530
  26. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · Tue Sep 22 13:33:56 2015 +0530
  27. e7ae6db Disable PL011 UART before configuring it by Juan Castillo · Thu Nov 26 14:52:15 2015 +0000
  28. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · Fri Aug 07 10:03:00 2015 +0530
  29. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · Fri Aug 21 15:56:02 2015 +0530
  30. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · Thu Jul 16 09:46:28 2015 +0530
  31. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530