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git01.mediatek.com / filogic / atf / 594919f3948fb3d115af01f782981e3e5d95b5ab / plat / rockchip / rk3399 / drivers / m0 / src
  1. df76b44 rk3399: m0: Fix compiler warnings. by Christoph Müllner · Mon Apr 15 21:42:29 2019 +0200
  2. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · Fri Apr 20 15:55:21 2018 +0800
  3. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  4. 397046c rockchip: rk3399: Move DQS drive strength setting to M0 by Derek Basehore · Wed Feb 01 18:09:13 2017 -0800
  5. b4bcc1d rockchip: Clean up header and referenced files by Xing Zheng · Fri Feb 24 16:26:11 2017 +0800
  6. fc0552d rockchip: rk3399: Don't wait for vblank in M0 for ddrfreq by Derek Basehore · Mon Jan 09 15:38:57 2017 -0800
  7. 2510366 rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs by Lin Huang · Fri Dec 30 11:50:01 2016 +0800
  8. 3b0eb7e rockchip: rk3399: check vop status when we wait dma finish flag by Lin Huang · Thu Dec 01 16:55:05 2016 +0800
  9. e7c2422 rockchip: rk3399: add stopwatch functions to m0 by Lin Huang · Wed Nov 30 16:57:08 2016 +0800
  10. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · Wed Oct 26 21:25:26 2016 +0800
  11. aae6be4 rockchip: update the raw read/write APIs for M0 by Xing Zheng · Mon Oct 24 21:06:25 2016 +0800
  12. b400374 rockchip: add M0 source code and build system for RK3399 by Caesar Wang · Wed Oct 12 08:10:12 2016 +0800