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git01.mediatek.com / filogic / atf / 551250c569a40b8839681f91053d3ace4aaebe84 / include / lib / cpus / aarch64 / cpu_macros.S
  1. caa2e05 fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 by Bipin Ravi · Wed Feb 23 23:45:50 2022 -0600
  2. f144157 Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS by Masahiro Yamada · Wed Apr 01 14:20:58 2020 +0900
  3. 94accd3 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · Tue Aug 20 15:51:24 2019 -0500
  4. a904487 Update macro to check need for CVE-2017-5715 mitigation by Antonio Nino Diaz · Tue Feb 12 11:25:02 2019 +0000
  5. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  6. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  7. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  8. b561536 plat/arm: relocate the jump_if_cpu_midr macro. by Deepak Pandey · Thu Oct 11 13:44:43 2018 +0530
  9. 26b8589 Remove integrity check in declare_cpu_ops_base by Roberto Vargas · Fri May 04 10:54:33 2018 +0100
  10. 67762d9 Remove .struct directive by Roberto Vargas · Tue May 01 09:54:54 2018 +0100
  11. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  12. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  13. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  14. 780cc95 Use PFR0 to identify need for mitigation of CVE-2017-5715 by Dimitris Papastamos · Mon Mar 12 13:27:02 2018 +0000
  15. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  16. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  17. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  18. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  19. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  20. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · Mon Dec 14 09:35:25 2015 +0000
  21. ea59668 Add header guards to asm macro files by Dan Handley · Wed Apr 01 17:34:24 2015 +0100
  22. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  23. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  24. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100[Renamed (89%) from include/lib/aarch64/cpu_macros.S]
  25. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100[Copied (63%) from lib/aarch64/cpu_helpers.S]
  26. c61399b Merge pull request #191 from danh-arm/jc/tf-issues/218 by danh-arm · Tue Aug 19 11:48:38 2014 +0100