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git01.mediatek.com
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filogic
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atf
/
536065a313010dd54fa3c25b905057b1bf0e0dae
/
lib
/
cpus
/
aarch64
/
cpu_helpers.S
667db2c
Merge changes from topic "bk/errata_refactor" into integration
by Manish Pandey
· 1 year, 5 months ago
cc30ccf
chore(cpus): remove redundant asserts
by Boyan Karatotev
· 1 year, 7 months ago
11b9b49
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
by Arvind Ram Prakash
· 1 year, 9 months ago
caa2e05
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
by Bipin Ravi
· 2 years, 6 months ago
7d0299f
fix: random typos in tf-a code base
by Olivier Deprez
· 3 years, 3 months ago
e1ecd23
arm_fpga: Add support for unknown MPIDs
by Javier Almansa Sobrino
· 4 years ago
718c876
lib: cpus: sanity check pointers before use
by Varun Wadekar
· 4 years, 11 months ago
94accd3
Neoverse N1 Errata Workaround 1542419
by laurenw-arm
· 5 years ago
4d034c5
Tegra: Support for scatterfile for the BL31 image
by Varun Wadekar
· 6 years ago
e0f9063
Sanitise includes across codebase
by Antonio Nino Diaz
· 6 years ago
ba51d9e
Add support for dynamic mitigation for CVE-2018-3639
by Dimitris Papastamos
· 6 years ago
570c06a
Rename symbols and files relating to CVE-2017-5715
by Dimitris Papastamos
· 6 years ago
efb1f33
Check presence of fix for errata 843419 in Cortex-A53
by Jonathan Wright
· 6 years ago
914757c
Fixup `SMCCC_ARCH_FEATURES` semantics
by Dimitris Papastamos
· 6 years ago
e0e9946
bl2-el3: Add BL2_EL3 image
by Roberto Vargas
· 7 years ago
815faa8
Use a callee-saved register to be AAPCS-compliant
by dp-arm
· 7 years ago
fa3cf0b
Use SPDX license identifiers
by dp-arm
· 7 years ago
7c65c1e
Remove build option `ASM_ASSERTION`
by Antonio Nino Diaz
· 7 years ago
00eefd9
Add workaround for ARM Cortex-A53 erratum 855873
by Andre Przywara
· 8 years ago
d5ec367
Report errata workaround status to console
by Jeenu Viswambharan
· 8 years ago
441bfdd
Use #ifdef for IMAGE_BL* instead of #if
by Masahiro Yamada
· 8 years ago
1f5f812
Correct system include order
by David Cunado
· 8 years ago
ee5eb80
Add provision to extend CPU operations at more levels
by Jeenu Viswambharan
· 8 years ago
6b28c57
Make cpu operations warning a VERBOSE print
by Soby Mathew
· 8 years ago
d481759
Disable non-temporal hint on Cortex-A53/57
by Sandrine Bailleux
· 9 years ago
a877c25
Add support to indicate size and end of assembly functions
by Kévin Petit
· 9 years ago
9b38fc8
Initialise cpu ops after enabling data cache
by Vikram Kanigiri
· 10 years ago
b5a6304
Fix the Cortex-A57 reset handler register usage
by Soby Mathew
· 10 years ago
36433d1
Call reset handlers upon BL3-1 entry.
by Yatharth Kochar
· 10 years ago
7d861ea
Invalidate the dcache after initializing cpu-ops
by Soby Mathew
· 10 years ago
c088433
Apply errata workarounds only when major/minor revisions match.
by Soby Mathew
· 10 years ago
38b4bc9
Add CPU specific crash reporting handlers
by Soby Mathew
· 10 years ago
8e2f287
Add CPU specific power management operations
by Soby Mathew
· 10 years ago
f1785fd
Add platform API for reset handling
by Soby Mathew
· 10 years ago
c704cbc
Introduce framework for CPU specific operations
by Soby Mathew
· 10 years ago