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git01.mediatek.com / filogic / atf / 4e04d4217b2178fb11b984c706b7531a6807b4bd / plat / nvidia / tegra / soc
  1. e98a146 Tegra132: set TZDRAM_BASE to 0xF5C00000 by Varun Wadekar · 9 years ago
  2. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · 9 years ago
  3. 0f3baa0 Tegra: Support for Tegra's T132 platforms by Varun Wadekar · 9 years ago
  4. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · 9 years ago
  5. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  6. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  7. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · 9 years ago
  8. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · 9 years ago
  9. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · 9 years ago
  10. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago