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git01.mediatek.com / filogic / atf / 47d8ecbeb8f592faaac7c0d89551062f5a0a6284 / plat / intel / soc / n5x / platform.mk
  1. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 1 year, 7 months ago
  2. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 2 years ago
  3. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years, 2 months ago
  4. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 3 years, 1 month ago
  5. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 4 months ago
  6. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years ago
  7. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 4 months ago