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git01.mediatek.com / filogic / atf / 47827116f9a5f7c49bc1bfd0c0bd45ca2786cc06 / include / drivers / nxp / dcfg
  1. ed6dc9b feat(nxp-dcfg): add Chassis 3 support by Biwen Li · Tue Jan 05 14:58:57 2021 +0800
  2. 2f7189b feat(nxp/driver/dcfg): add some macro definition by Jiafei Pan · Thu Oct 21 17:07:18 2021 +0800
  3. e85dbdb feat(nxp/driver/dcfg): add gic address align register definition by Jiafei Pan · Thu Oct 21 16:01:47 2021 +0800
  4. d59bd1a fix(nxp/scfg): fix endianness checking by Jiafei Pan · Sun Sep 26 15:51:15 2021 +0800
  5. 67a9890 feat(driver/nxp/dcfg): define RSTCR_RESET_REQ by Jiafei Pan · Fri Sep 10 19:10:47 2021 +0800
  6. b27ac80 refactor(plat/nxp): refine api to read SVR register by Jiafei Pan · Tue Jul 20 17:14:32 2021 +0800
  7. 7834b46 refactor: moved drivers hdr files to include/drivers/nxp by Pankaj Gupta · Thu Mar 25 15:15:52 2021 +0530