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git01.mediatek.com / filogic / atf / 4475acee5c4970795496aa84d39b5aaab08c5ce5
  1. 4475ace Merge "fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32" into integration by Madhukar Pappireddy · Wed Dec 22 23:57:16 2021 +0100
  2. 2863e0a Merge "fix(fiptool): respect OPENSSL_DIR" into integration by Madhukar Pappireddy · Wed Dec 22 22:24:44 2021 +0100
  3. 8341ddd Merge "fix(trp): Distinguish between cold and warm boot" into integration by Bipin Ravi · Wed Dec 22 21:13:03 2021 +0100
  4. c16d12e Merge changes from topic "uart1_console" into integration by Madhukar Pappireddy · Wed Dec 22 19:18:15 2021 +0100
  5. ef681ea Merge changes from topic "clock_framework" into integration by Madhukar Pappireddy · Wed Dec 22 19:17:57 2021 +0100
  6. 0280eb4 Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration by Madhukar Pappireddy · Wed Dec 22 19:16:55 2021 +0100
  7. 1917f32 Merge "fix(fiptool): avoid packing the zero size images in the FIP" into integration by Madhukar Pappireddy · Wed Dec 22 15:32:14 2021 +0100
  8. 1a9b827 Merge "fix(errata): workaround for Cortex X2 erratum 2058056" into integration by Madhukar Pappireddy · Wed Dec 22 15:23:00 2021 +0100
  9. 7d91767 fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32 by Yann Gautier · Fri Nov 19 11:35:46 2021 +0100
  10. a205a5c feat(st): use newly introduced clock framework by Yann Gautier · Mon Aug 30 15:06:54 2021 +0200
  11. 8aac307 feat(clk): add a minimal clock framework by Gabriel Fernandez · Tue Oct 13 09:36:25 2020 +0200
  12. e91b4c2 feat(versal): add UART1 as console by Venkatesh Yadav Abbarapu · Sun Dec 19 21:36:23 2021 -0700
  13. 0bd80de feat(zynqmp): add uart1 as console by Venkatesh Yadav Abbarapu · Sun Dec 19 21:32:00 2021 -0700
  14. 047d85e feat(plat/mediatek/mt8186): add reboot function for PSCI by Rex-BC Chen · Mon Nov 22 18:14:38 2021 +0800
  15. dc0f9f7 feat(plat/mdeiatek/mt8186): add power-off function for PSCI by Rex-BC Chen · Mon Nov 22 17:55:56 2021 +0800
  16. 4a1570a feat(plat/mediatek/mt8186): apply erratas for MT8186 by Rex-BC Chen · Thu Nov 25 18:55:04 2021 +0800
  17. ba7b7d2 feat(plat/mediatek/mt8186): add MCDI drivers by developer · Sun Nov 14 10:14:45 2021 +0800
  18. c3dabd8 feat(plat/mediatek/mt8186): add CPU hotplug by developer · Mon Nov 08 11:30:40 2021 +0800
  19. ad04044 feat(plat/mediatek/mt8186): add RTC drivers by Yuchen Huang · Fri Nov 12 16:56:33 2021 +0800
  20. f44c0df fix(plat/mediatek/mt8186): extend MMU region size by Rex-BC Chen · Tue Nov 09 13:12:03 2021 +0800
  21. 63582ec feat(plat/mediatek/mt8186): add DCM driver by Edward-JW Yang · Mon Nov 01 20:20:18 2021 +0800
  22. 532016e feat(plat/mediatek/mt8186): add pinctrl support by Guodong Liu · Fri Oct 15 16:52:18 2021 +0800
  23. fd835f9 feat(plat/mediatek/mt8186): add sys_cirq support by Zhengnan Chen · Tue Oct 12 17:05:49 2021 +0800
  24. ccd2600 feat(plat/mediatek/mt8186): initialize GIC by Christine Zhu · Mon Oct 11 21:29:58 2021 +0800
  25. abd9ecf feat(plat/mediatek/mt8186): add SiP service by Rex-BC Chen · Wed Oct 06 19:25:50 2021 +0800
  26. 4ac7a41 feat(plat/mediatek/mt8186): add pwrap and pmic driver by James Lo · Wed Oct 06 18:12:30 2021 +0800
  27. 0bee8f9 feat(plat/mediatek/mt8186): initialize delay_timer by Rex-BC Chen · Wed Oct 06 19:00:13 2021 +0800
  28. d24c05d feat(plat/mediatek/mt8186): initialize systimer by Rex-BC Chen · Wed Oct 06 18:55:53 2021 +0800
  29. fb70fb4 feat(plat/mediatek/mt8186): add EMI MPU basic driver by Penny Jan · Sun Oct 03 10:11:04 2021 +0800
  30. ab853c2 Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integration by Bipin Ravi · Wed Dec 22 01:12:32 2021 +0100
  31. 28e8cfe Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration by Bipin Ravi · Wed Dec 22 01:10:54 2021 +0100
  32. 5e2abbe Merge "fix(doc): update TF-A v2.7 release date in the release information page" into integration by Mark Dykes · Tue Dec 21 19:08:44 2021 +0100
  33. f6c37de fix(errata): workaround for Cortex X2 erratum 2058056 by johpow01 · Fri Dec 03 11:27:33 2021 -0600
  34. 68edfdc fix(doc): update TF-A v2.7 release date in the release information page by Bipin Ravi · Tue Dec 21 09:14:48 2021 -0600
  35. 0624d73 fix(fiptool): avoid packing the zero size images in the FIP by Manish V Badarkhe · Sat Dec 18 11:26:25 2021 +0000
  36. d001b27 Merge "fix(stm32mp1): correct include order" into integration by Madhukar Pappireddy · Fri Dec 17 20:04:33 2021 +0100
  37. 0afef36 fix(errata): workaround for Cortex X2 erratum 2002765 by johpow01 · Thu Dec 02 13:25:50 2021 -0600
  38. 40f4133 Merge changes from topic "morello_plat_support" into integration by Madhukar Pappireddy · Fri Dec 17 15:10:52 2021 +0100
  39. 0c81088 fix(stm32mp1): correct include order by Yann Gautier · Fri Dec 17 09:53:04 2021 +0100
  40. 15f10bd fix(errata): workaround for Cortex X2 erratum 2083908 by johpow01 · Wed Dec 01 17:40:39 2021 -0600
  41. 8e9c9c5 Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integration by Madhukar Pappireddy · Thu Dec 16 17:18:01 2021 +0100
  42. 05489b9 Merge "fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags" into integration by Olivier Deprez · Thu Dec 16 16:34:28 2021 +0100
  43. b7682b4 feat(morello): expose scmi protocols in fdts by Anurag Koul · Fri Dec 03 10:16:47 2021 +0000
  44. 118ad71 fix(morello): change the AP runtime UART address by Chandni Cherukuri · Thu Dec 02 11:22:59 2021 +0530
  45. 066afc2 feat(morello): add support for nt_fw_config by sah01 · Thu Nov 18 10:04:27 2021 +0000
  46. 3c5bb04 feat(morello): split platform_info sds struct by sah01 · Thu Dec 02 06:37:04 2021 +0000
  47. 5887612 feat(morello): add changes to enable TBBR boot by Manoj Kumar · Sun Jan 10 16:12:24 2021 +0000
  48. 460e377 Merge "docs(ff-a): boot order field of SPs manifest" into integration by Madhukar Pappireddy · Thu Dec 16 15:17:08 2021 +0100
  49. d4d951a feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support by Gary Morrison · Wed Nov 10 14:40:15 2021 -0600
  50. 70c9c0b fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags by Jayanth Dodderi Chidanand · Wed Dec 15 16:52:10 2021 +0000
  51. 855fc88 docs(ff-a): boot order field of SPs manifest by J-Alves · Tue Dec 14 16:02:27 2021 +0000
  52. 9952970 feat(morello): add DTS for Morello SoC platform by Manoj Kumar · Wed Sep 15 12:42:49 2021 +0530
  53. dff7f6c feat(morello): configure DMC-Bing mode by Chandni Cherukuri · Tue Nov 30 20:35:35 2021 +0530
  54. b19e62a feat(morello): zero out the DDR memory space by Manoj Kumar · Thu Aug 26 10:49:02 2021 +0530
  55. c7ea5f3 feat(morello): add TARGET_PLATFORM flag by Manoj Kumar · Thu Aug 26 10:56:16 2021 +0530
  56. 6f749e2 fix(morello): fix SoC reference clock frequency by Anurag Koul · Wed Aug 25 19:34:20 2021 +0530
  57. 0e6ddbc fix(arm): use PLAT instead of TARGET_PLATFORM by Chandni Cherukuri · Sat Dec 11 14:16:17 2021 +0530
  58. 8bac9f9 Merge changes from topic "fconf_get_index" into integration by Madhukar Pappireddy · Tue Dec 14 20:58:09 2021 +0100
  59. 64edaa3 Merge changes from topic "st_uart_update" into integration by Madhukar Pappireddy · Tue Dec 14 18:25:39 2021 +0100
  60. 50746c8 fix(trp): Distinguish between cold and warm boot by Mark Dykes · Wed Dec 01 15:08:02 2021 -0600
  61. 3d8497c feat(st): protect UART during platform init by Yann Gautier · Mon Oct 18 16:06:22 2021 +0200
  62. 414f17c feat(stm32mp1): update console management for SP_min by Yann Gautier · Mon Oct 18 15:50:05 2021 +0200
  63. 66baa96 refactor(stm32mp1): improve console management in BL2 by Yann Gautier · Mon Oct 18 14:01:00 2021 +0200
  64. 7a81912 feat(plat/st): add a function to configure console by Yann Gautier · Mon Oct 18 15:26:33 2021 +0200
  65. aaee061 feat(stm32mp1): add stm32_get_boot_interface function by Yann Gautier · Wed Dec 16 12:04:06 2020 +0100
  66. 6eef525 refactor(stm32mp1): move stm32_save_boot_interface() by Yann Gautier · Fri Dec 10 17:04:40 2021 +0100
  67. cd16df3 fix(stm32mp1): deconfigure UART RX pins by Yann Gautier · Fri Jun 04 14:04:05 2021 +0200
  68. 2b79c37 feat(stm32_gpio): add a function to reset a pin by Yann Gautier · Fri Jun 11 10:54:56 2021 +0200
  69. 27f589d refactor(stm32mp1): sort compilation flags by Yann Gautier · Fri Oct 15 17:59:38 2021 +0200
  70. 19cdaa8 feat(stm32mp1): add sign-compare warning by Yann Gautier · Tue Nov 10 15:09:55 2020 +0100
  71. 0e2c001 Merge "fix(scmi): make msg_header variable volatile" into integration by Madhukar Pappireddy · Mon Dec 13 20:12:02 2021 +0100
  72. fd64835 feat(stm32mp1): skip TOS_FW_CONFIG if not in FIP by Yann Gautier · Mon Dec 13 15:24:41 2021 +0100
  73. 5a57e25 feat(fconf): add a helper to get image index by Yann Gautier · Mon Dec 13 15:22:45 2021 +0100
  74. 2d17705 Merge changes from topic "jc/AMUv1" into integration by Manish Pandey · Mon Dec 13 13:52:37 2021 +0100
  75. 0f5e0bb Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration by Madhukar Pappireddy · Fri Dec 10 19:07:40 2021 +0100
  76. 683122e Merge changes from topic "a3700-comphy-fixes-1" into integration by Madhukar Pappireddy · Fri Dec 10 16:06:16 2021 +0100
  77. 7e3035e Merge changes from topic "mb_critical_data" into integration by Manish Pandey · Fri Dec 10 14:37:06 2021 +0100
  78. 4959cc2 Merge "feat(stm32mp1): preserve the PLL4 settings for USB boot" into integration by Manish Pandey · Fri Dec 10 14:19:15 2021 +0100
  79. 76ff363 docs(build-options): add build macros for features FGT,AMUv1 and ECV by Jayanth Dodderi Chidanand · Sun Dec 05 19:21:14 2021 +0000
  80. 13ae0f4 fix(amu): fault handling on EL2 context switch by Jayanth Dodderi Chidanand · Thu Nov 25 14:59:30 2021 +0000
  81. 3764d34 Merge "fix(rmmd/sve): enable/disable SVE/FPU for Realms" into integration by Alexei Fedorov · Fri Dec 10 13:28:48 2021 +0100
  82. f9d518a feat(plat/zynqmp): disable the -mbranch-protection flag by Venkatesh Yadav Abbarapu · Mon Dec 06 21:28:34 2021 -0700
  83. 2e9e015 Merge "fix(rmmd): align RMI and GTSI FIDs with SMCCC" into integration by Alexei Fedorov · Fri Dec 10 12:20:36 2021 +0100
  84. 957d7ea Merge "refactor(measured-boot): add generic macros for using Crypto library" into integration by Madhukar Pappireddy · Fri Dec 10 01:25:26 2021 +0100
  85. c25225a fix(rmmd/sve): enable/disable SVE/FPU for Realms by Subhasish Ghosh · Thu Dec 09 15:41:37 2021 +0000
  86. 0131988 Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration by Madhukar Pappireddy · Thu Dec 09 15:03:19 2021 +0100
  87. 938e0dd Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration by Madhukar Pappireddy · Thu Dec 09 15:03:06 2021 +0100
  88. 1132db8 refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants by Marek Behún · Wed Dec 08 01:33:38 2021 +0100
  89. b531ca7 refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants by Marek Behún · Wed Dec 08 01:29:50 2021 +0100
  90. e58e733 refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants by Marek Behún · Wed Dec 08 01:27:38 2021 +0100
  91. d6d3247 refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants by Marek Behún · Wed Dec 08 01:24:36 2021 +0100
  92. d0da334 refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants by Marek Behún · Wed Dec 08 01:20:50 2021 +0100
  93. 6355cdb refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants by Marek Behún · Wed Dec 08 00:15:29 2021 +0100
  94. 5a90dc3 refactor(drivers/marvell/comphy-3700): unify Generation Settings register values by Marek Behún · Wed Dec 08 01:12:00 2021 +0100
  95. ff8afbe refactor(drivers/marvell/comphy-3700): unify Generation Settings register names by Marek Behún · Wed Dec 08 00:52:28 2021 +0100
  96. 781babd4 refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes by Marek Behún · Wed Dec 08 00:46:00 2021 +0100
  97. 0284c8a refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes by Marek Behún · Wed Dec 08 00:37:34 2021 +0100
  98. 4457e65b refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG by Marek Behún · Thu Dec 02 20:04:57 2021 +0100
  99. 88315c5 refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition by Marek Behún · Thu Dec 02 20:29:30 2021 +0100
  100. 9a0e4d9 refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G by Marek Behún · Wed Dec 01 13:45:42 2021 +0100