1. f8fec36 Add Xilinx ZynqMP IPI mailbox service by Wendy Liang · Wed Sep 06 09:39:55 2017 -0700
  2. 3aebacf Introduce ZynqMP IPI implementation by Wendy Liang · Wed Sep 13 11:02:42 2017 -0700
  3. c5b0c0f Do not enable SVE on pre-v8.2 platforms by David Cunado · Tue Oct 31 23:19:21 2017 +0000
  4. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  5. ba8309d zynqmp: Enable workaround for errata 855873 by Soren Brinkmann · Thu Apr 06 11:44:27 2017 -0700
  6. 230011c Move plat/common source file definitions to generic Makefiles by dp-arm · Tue Mar 07 11:02:47 2017 +0000
  7. 8cf895c zynqmp: add "override" directive to mandatory options by Masahiro Yamada · Mon Dec 19 17:41:47 2016 +0900
  8. 493bf33 Fix incorrect copyright notices by Antonio Nino Diaz · Wed Dec 14 14:31:32 2016 +0000
  9. 92b8932 zynqmp: Set RESET_TO_BL31 through platform.mk by Soren Brinkmann · Wed Jul 06 15:11:31 2016 -0700
  10. e5bdcaa zynqmp: Add support for generic_delay_timer by Soren Brinkmann · Wed Jun 22 09:02:56 2016 -0700
  11. 1723113 Migrate platform makefile to new console driver location by Soby Mathew · Mon Aug 08 12:33:06 2016 +0100
  12. 0f553dc Merge pull request #667 from soby-mathew/sm/PSCI_lib by danh-arm · Mon Jul 25 12:29:52 2016 +0100
  13. 0eb965b Move `arm_common.c` out of aarch64 folder by Soby Mathew · Thu Jul 07 08:45:56 2016 +0100
  14. f6c4108 Include `plat_psci_common.c` from the new location by Soby Mathew · Tue May 03 12:31:18 2016 +0100
  15. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · Fri Jul 08 14:45:14 2016 -0700
  16. 99c0d7b zynqmp: Add option to select between Cadence UARTs by Soren Brinkmann · Fri Jun 10 09:57:14 2016 -0700
  17. ef8f559 zynqmp: FSBL->ATF handover by Michal Simek · Mon Jun 15 14:22:50 2015 +0200
  18. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · Thu Apr 14 10:27:00 2016 -0700
  19. cc037c1 Migrate platform ports to the new xlat_tables library by Soby Mathew · Fri Apr 08 16:42:58 2016 +0100
  20. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800