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git01.mediatek.com / filogic / atf / 43a7bf4d4628f049ead65115edf34a17dde9df25 / plat / xilinx / zynqmp / include
  1. c150312 Update ULL() macro and instances of ull to comply with MISRA by David Cunado · 7 years ago
  2. 9bde130 zynqmp: Migrate to using interrupt properties by Jeenu Viswambharan · 7 years ago
  3. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  4. 6a9e03e zynqmp: Migrate to new address space macros by Soren Brinkmann · 8 years ago
  5. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · 8 years ago
  6. 7ac746c zynqmp: Increase MAX_XLAT_TABLES by Soren Brinkmann · 8 years ago
  7. 802ba1d zynqmp: Change default BL31 address space by Soren Brinkmann · 8 years ago
  8. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · 8 years ago
  9. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · 9 years ago
  10. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · 9 years ago
  11. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · 9 years ago
  12. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · 9 years ago