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git01.mediatek.com
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filogic
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atf
/
43a7bf4d4628f049ead65115edf34a17dde9df25
/
plat
/
rockchip
/
rk3399
/
drivers
/
dram
/
dfs.c
ff957ed
plat: fix switch statements to comply with MISRA rules
by Jonathan Wright
· 6 years ago
e363146
Fix order of remaining platform #includes
by Isla Mitchell
· 7 years ago
e22d31a
rockchip/rk3399: fix DRAM gate training issue
by Lin Huang
· 8 years ago
fa3cf0b
Use SPDX license identifiers
by dp-arm
· 7 years ago
509f379
rockchip/rk3399: changed printf/tf_printf for console output
by Caesar Wang
· 7 years ago
be2a895
rockchip: rk3399: Use tFC value instead of tRFC value
by Derek Basehore
· 8 years ago
b07dfeb
rockchip: rk3399: Fix CAS latency setting
by Derek Basehore
· 8 years ago
035d6d6
rockchip: rk3399: disable training modules after DDR DFS
by Xing Zheng
· 8 years ago
397046c
rockchip: rk3399: Move DQS drive strength setting to M0
by Derek Basehore
· 8 years ago
b734ba5
rockchip: rk3399: Remove dram dfs optimization
by Derek Basehore
· 8 years ago
b4a7676
rockchip: rk3399: improve the m0 enable flow
by Lin Huang
· 8 years ago
52512c2
rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0
by Lin Huang
· 8 years ago
dc8e82e
rockchip: rk3399: enable CA training when do ddr dfs
by Lin Huang
· 8 years ago
0e8909d
rockchip: rk3399: Enable per CS training at 666MHz
by Derek Basehore
· 8 years ago
e13bc54
rockchip: rk3399: add support for ddrfreq suspend/resume
by Derek Basehore
· 8 years ago
93280b7
rk3399: dram: use PMU M0 to do ddr frequency scaling
by Xing Zheng
· 8 years ago
b106512
rk3399: dram: making phy into dll bypass mode at low frequency
by Derek Basehore
· 8 years ago
ff461d0
rockchip: rk3399: dram: remove dram_init and dts_timing_receive function
by Derek Basehore
· 8 years ago
8bc1667
rockchip: Change dmc register accesses to ATF style for rk3399
by Caesar Wang
· 8 years ago
a845690
rockchip: Break out common dram code for rk3399
by Caesar Wang
· 8 years ago