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git01.mediatek.com / filogic / atf / 3d18a933ad8f6e83408d6bb60ef130f317290a12 / plat / xilinx / versal / versal_gicv3.c
  1. 6da8794 fix(xilinx): rename macros to align with ARM by Jay Buddhabhatti · Thu Oct 05 05:21:50 2023 -0700
  2. 536e110 chore(xilinx): reorder include files as per TF-A guidelines by Prasad Kummari · Thu Jun 22 10:50:02 2023 +0530
  3. 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · Fri Apr 14 08:43:51 2023 +0200
  4. 6a44ad0 refactor(xilinx): rename gic macros to make common by Jay Buddhabhatti · Tue Feb 28 01:23:04 2023 -0800
  5. 33bfc5e build: always prefix section names with `.` by Chris Kay · Tue Feb 14 11:30:04 2023 +0000
  6. bde8759 fix(versal): resolve the misra 4.6 warnings by Venkatesh Yadav Abbarapu · Tue May 24 11:11:12 2022 +0530
  7. 6940996 plat: xilinx: versal: Move versal_private.h to include directory by Tejas Patel · Fri Dec 14 00:55:29 2018 -0800
  8. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  9. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · Tue Sep 25 18:44:58 2018 +0530