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git01.mediatek.com / filogic / atf / 3c3121879726179cfa82becce0ffe1c2e8db928d / services
  1. 9616838 PSCI: Add SYSTEM_SUSPEND API support by Soby Mathew · 10 years ago
  2. 33e7d6a Fix integer extension in mpidr_set_aff_inst() by Andrew Thoelke · 9 years ago
  3. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · 9 years ago
  4. acde8b0 Rationalize reset handling code by Sandrine Bailleux · 9 years ago
  5. 22fa7e4 PSCI: Set ON_PENDING state early during CPU_ON by Soby Mathew · 9 years ago
  6. ebfeae9 Pass arguments/results between EL3/S-EL1 via CPU registers (x0-x7) by Varun Wadekar · 10 years ago
  7. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · 10 years ago
  8. 2eb68ca Merge pull request #280 from vwadekar/tlkd-fixed-v3 by danh-arm · 10 years ago
  9. b539b6c Open/Close TA sessions, send commands/events to TAs by Varun Wadekar · 10 years ago
  10. 968c029 Preempt/Resume standard function ID calls by Varun Wadekar · 10 years ago
  11. 97625e3 Translate secure/non-secure virtual addresses by Varun Wadekar · 10 years ago
  12. a97535f Register NS shared memory for SP's activity logs and TA sessions by Varun Wadekar · 10 years ago
  13. 3d4e6a5 Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd) by Varun Wadekar · 10 years ago
  14. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · 10 years ago
  15. a64a854 Fix violations to the coding style by Sandrine Bailleux · 10 years ago
  16. 2b7de2b Export maximum affinity using PLATFORM_MAX_AFFLVL macro by Soby Mathew · 10 years ago
  17. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 10 years ago
  18. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · 10 years ago
  19. 61e615b Verify capabilities before handling PSCI calls by Soby Mathew · 10 years ago
  20. 6cdddaf Implement PSCI_FEATURES API by Soby Mathew · 10 years ago
  21. 110fe36 Rework the PSCI migrate APIs by Soby Mathew · 10 years ago
  22. 26fb90e Return success if an interrupt is seen during PSCI CPU_SUSPEND by Soby Mathew · 10 years ago
  23. 74e52a7 Validate power_state and entrypoint when executing PSCI calls by Soby Mathew · 10 years ago
  24. f512157 Save 'power_state' early in PSCI CPU_SUSPEND call by Soby Mathew · 10 years ago
  25. 8595b87 Rework internal API to save non-secure entry point info by Soby Mathew · 10 years ago
  26. 5f2c1b3 PSCI: Check early for invalid CPU state during CPU ON by Soby Mathew · 10 years ago
  27. ffb4ab1 Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops by Soby Mathew · 10 years ago
  28. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · 10 years ago
  29. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · 10 years ago
  30. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · 10 years ago
  31. 2b69750 Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl() by Soby Mathew · 10 years ago
  32. e2b2d8f Fix the array size of mpidr_aff_map_nodes_t. by Soby Mathew · 10 years ago
  33. c288886 Add opteed based on tspd by Jens Wiklander · 10 years ago
  34. 8e2f287 Add CPU specific power management operations by Soby Mathew · 10 years ago
  35. 56bcdc2 Miscellaneous PSCI code cleanups by Achin Gupta · 10 years ago
  36. f6b9e99 Add APIs to preserve highest affinity level in OFF state by Achin Gupta · 10 years ago
  37. cab78e4 Rework state management in the PSCI implementation by Achin Gupta · 10 years ago
  38. f3ccbab Add PSCI service specific per-CPU data by Achin Gupta · 10 years ago
  39. 4dc4a47 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · 10 years ago
  40. 9e46188 Merge pull request #189 from achingupta/ag/tf-issues#153 by Dan Handley · 10 years ago
  41. 4fd2f5c Clarify platform porting interface to TSP by Dan Handley · 10 years ago
  42. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · 10 years ago
  43. 6dc22e3 Merge pull request #178 from soby-mathew/sm/optmize_el3_context by danh-arm · 10 years ago
  44. 4e81341 Support asynchronous method for BL3-2 initialization by Vikram Kanigiri · 10 years ago
  45. 9d70f0f Rework the TSPD setup code by Vikram Kanigiri · 10 years ago
  46. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · 10 years ago
  47. 5cd545d Merge pull request #177 from jcastillo-arm/jc/tf-issues/096 by danh-arm · 10 years ago
  48. f558cac Rework incorrect use of assert() and panic() in codebase by Juan Castillo · 10 years ago
  49. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · 10 years ago
  50. 9c60d80 Remove the concept of coherent stacks by Achin Gupta · 10 years ago
  51. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · 10 years ago
  52. e998254 Make enablement of the MMU more flexible by Achin Gupta · 10 years ago
  53. 2bc0785 Remove current CPU mpidr from PSCI common code by Andrew Thoelke · 10 years ago
  54. 3c74a44 Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2 by danh-arm · 10 years ago
  55. 42970b0 Merge pull request #147 from athoelke/at/remove-bakery-mpidr by danh-arm · 10 years ago
  56. 2d55240 Remove all checkpatch errors from codebase by Juan Castillo · 10 years ago
  57. 958cc02 Remove calling CPU mpidr from bakery lock API by Andrew Thoelke · 10 years ago
  58. fb06094 Merge pull request #145 from athoelke/at/psci-memory-optimization-v2 by danh-arm · 10 years ago
  59. dc589aa Merge pull request #144 from athoelke/at/init-context-v2 by danh-arm · 10 years ago
  60. 56f4470 Correctly dimension the PSCI aff_map_node array by Andrew Thoelke · 10 years ago
  61. e9a0d11 Eliminate psci_suspend_context array by Andrew Thoelke · 10 years ago
  62. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · 10 years ago
  63. 4af473c Merge pull request #140 from athoelke/at/psci_smc_handler by danh-arm · 10 years ago
  64. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · 10 years ago
  65. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · 10 years ago
  66. a2f6553 Provide cm_get/set_context() for current CPU by Andrew Thoelke · 10 years ago
  67. 89a3c84 PSCI SMC handler improvements by Andrew Thoelke · 10 years ago
  68. 93c89ec Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · 10 years ago
  69. 459df4c Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 into for-v0.4 by Dan Handley · 10 years ago
  70. 701fea7 Further renames of platform porting functions by Dan Handley · 10 years ago
  71. 3d57851 Fixup Standard SMC Resume Handling by Soby Mathew · 10 years ago
  72. b226a4d Add enable mmu platform porting interfaces by Dan Handley · 10 years ago
  73. ed6ff95 Split platform.h into separate headers by Dan Handley · 10 years ago
  74. 60b13e3 Remove unused data declarations by Dan Handley · 10 years ago
  75. a17fefa Remove extern keyword from function declarations by Dan Handley · 10 years ago
  76. 332ff85 Merge pull request #104 from athoelke:at/tsp-entrypoints-v2 by Andrew Thoelke · 10 years ago
  77. 077193f Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2 by Andrew Thoelke · 10 years ago
  78. 58484d4 Merge pull request #102 from achingupta:ag/tf-issues#104-v2 by Andrew Thoelke · 10 years ago
  79. 29c7ae1 Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3 by Andrew Thoelke · 10 years ago
  80. 1c5630d Merge pull request #67 from achingupta:ag/psci_standby_bug_fix by Andrew Thoelke · 10 years ago
  81. 891c4ca Use a vector table for TSP entrypoints by Andrew Thoelke · 10 years ago
  82. 9f71f70 Non-Secure Interrupt support during Standard SMC processing in TSP by Soby Mathew · 10 years ago
  83. aeaab68 Add S-EL1 interrupt handling support in the TSPD by Achin Gupta · 10 years ago
  84. 405406d Use secure timer to generate S-EL1 interrupts by Achin Gupta · 10 years ago
  85. 9cf2bb7 Introduce interrupt handling framework in BL3-1 by Achin Gupta · 10 years ago
  86. 27b895e Add context library API to change a bit in SCR_EL3 by Achin Gupta · 11 years ago
  87. 18d6eaf Rework 'state' field usage in per-cpu TSP context by Achin Gupta · 11 years ago
  88. d8c9d26 Rework memory information passing to BL3-x images by Vikram Kanigiri · 10 years ago
  89. da56743 Populate BL31 input parameters as per new spec by Vikram Kanigiri · 11 years ago
  90. 9851e42 Introduce macros to manipulate the SPSR by Vikram Kanigiri · 10 years ago
  91. 5e5c207 Rework BL3-1 unhandled exception handling and reporting by Soby Mathew · 11 years ago
  92. 42c5280 Fix broken standby state implementation in PSCI by Achin Gupta · 10 years ago
  93. 74a62b3 fvp: Provide per-EL MMU setup functions by Sandrine Bailleux · 10 years ago
  94. 9ceff0f Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1 by danh-arm · 10 years ago
  95. 6c5192a Preserve x19-x29 across world switch for exception handling by Soby Mathew · 11 years ago
  96. f977ed8 Access system registers directly in assembler by Andrew Thoelke · 11 years ago
  97. 42e75a7 Correct usage of data and instruction barriers by Andrew Thoelke · 11 years ago
  98. a4cb68e Remove variables from .data section by Dan Handley · 11 years ago
  99. 2bd4ef2 Reduce deep nesting of header files by Dan Handley · 11 years ago
  100. e2712bc Always use named structs in header files by Dan Handley · 11 years ago