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bl31
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aarch64
7538ef9
feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS
by Jorge Ramirez-Ortiz
· Fri Apr 15 11:46:47 2022 +0200
928747f
fix(el3-runtime): set unset pstate bits to default
by Daniel Boulby
· Tue May 25 18:09:34 2021 +0100
95fb1aa
refactor(el3-runtime): add prepare_el3_entry func
by Daniel Boulby
· Wed Jan 19 11:20:05 2022 +0000
9d13402
refactor(gpt): productize and refactor GPT library
by johpow01
· Wed Jun 16 17:57:28 2021 -0500
8e2e24b
feat(rme): add GPT Library
by Zelalem Aweke
· Tue Jul 13 14:05:20 2021 -0500
4d666ac
feat(rme): add Realm security state definition
by Zelalem Aweke
· Thu Jul 08 17:13:09 2021 -0500
fba2572
Fix exception handlers in BL31: Use DSB to synchronize pending EA
by Madhukar Pappireddy
· Fri Jul 24 03:27:12 2020 -0500
e07e808
runtime_exceptions: Update AT speculative workaround
by Manish V Badarkhe
· Thu Jul 23 12:43:25 2020 +0100
813c9f9
Fix crash dump for lower EL
by Alexei Fedorov
· Tue Mar 03 13:31:58 2020 +0000
b8f26e9
Make PAC demangling more generic
by Alexei Fedorov
· Thu Feb 06 17:11:03 2020 +0000
f4e6ea6
Changes necessary to support SEPARATE_NOBITS_REGION feature
by Madhukar Pappireddy
· Mon Jan 27 15:32:15 2020 -0600
0f7e601
Prevent speculative execution past ERET
by Anthony Steinhauser
· Tue Jan 07 15:44:06 2020 -0800
aa4fd60
Merge changes from topic "bs/pmf32" into integration
by György Szing
· Fri Dec 20 10:33:43 2019 +0000
fa01598
aarch64: Fix stack pointer maintenance on EA handling path
by Jan Dabros
· Mon Dec 02 13:30:03 2019 +0100
78dc10c
pmf: Make the runtime instrumentation work on AArch32
by Bence Szépkúti
· Thu Nov 07 12:09:24 2019 +0100
c825768
PIE: make call to GDT relocation fixup generalized
by Manish Pandey
· Tue Nov 26 11:34:17 2019 +0000
94accd3
Neoverse N1 Errata Workaround 1542419
by laurenw-arm
· Tue Aug 20 15:51:24 2019 -0500
f41355c
Refactor ARMv8.3 Pointer Authentication support code
by Alexei Fedorov
· Fri Sep 13 14:11:59 2019 +0100
83e0488
Add UBSAN support and handlers
by Justin Chadwell
· Tue Aug 20 11:01:52 2019 +0100
7690382
Move assembly newline function into common debug code
by Justin Chadwell
· Tue Aug 20 10:58:49 2019 +0100
c7a7cc3
Merge "AArch64: Disable Secure Cycle Counter" into integration
by Paul Beesley
· Fri Aug 23 11:26:57 2019 +0000
503bbf3
AArch64: Disable Secure Cycle Counter
by Alexei Fedorov
· Tue Aug 13 15:17:53 2019 +0100
c4dfb3b
AArch64: Align crash reporting output
by Alexei Fedorov
· Mon Jul 29 13:34:07 2019 +0100
b5b903c
Fix BL31 crash reporting on AArch64 only machines
by Imre Kis
· Mon Jul 22 11:56:45 2019 +0200
90f2e88
Add support for Branch Target Identification
by Alexei Fedorov
· Fri May 24 12:17:09 2019 +0100
d87233a
Rework smc_unknown return code path in smc_handler
by Madhukar Pappireddy
· Wed May 08 15:41:41 2019 -0500
dd894cc
Fix restoration of PAuth context
by Alexei Fedorov
· Fri Apr 05 13:44:30 2019 +0100
81de7ab
PIE: Fix reloc at the beginning of bl31 entrypoint
by Louis Mayencourt
· Fri Mar 22 16:33:23 2019 +0000
3287c4f
Restore PAuth context in case of unknown SMC call
by Alexei Fedorov
· Mon Mar 18 15:59:34 2019 +0000
e71d26c
BL31: Enable pointer authentication support in warm boot path
by Alexei Fedorov
· Wed Mar 06 11:15:51 2019 +0000
47a9064
BL31: Enable pointer authentication support
by Antonio Nino Diaz
· Thu Jan 31 11:01:26 2019 +0000
25cda67
Add support for pointer authentication
by Antonio Nino Diaz
· Tue Feb 19 11:53:51 2019 +0000
594811b
Add ARMv8.3-PAuth registers to CPU context
by Antonio Nino Diaz
· Thu Jan 31 11:58:00 2019 +0000
0e402d3
Remove support for the SMC Calling Convention 2.0
by Antonio Nino Diaz
· Wed Jan 30 16:01:49 2019 +0000
e0f9063
Sanitise includes across codebase
by Antonio Nino Diaz
· Fri Dec 14 00:18:21 2018 +0000
f939a6a
SPM: Introduce SMC handlers for SPCI and SPRT
by Antonio Nino Diaz
· Thu Nov 08 14:12:40 2018 +0000
d1198ad
BL31: Use helper function to save registers in SMC handler
by Soby Mathew
· Fri Nov 16 15:43:34 2018 +0000
4e28c20
PIE: Position Independant Executable support for BL31
by Soby Mathew
· Sun Oct 14 08:09:22 2018 +0100
f0b14cf
Remove some MISRA defects in common code
by Antonio Nino Diaz
· Thu Oct 04 09:55:23 2018 +0100
911fcc9
RAS: Introduce handler for EL3 EAs
by Jeenu Viswambharan
· Fri Jul 06 16:50:06 2018 +0100
93bc4bd
RAS: Introduce handler for Double Faults
by Jeenu Viswambharan
· Thu May 17 11:24:01 2018 +0100
9d4c9c1
RAS: Introduce handler for Uncontainable errors
by Jeenu Viswambharan
· Thu May 17 09:52:36 2018 +0100
476c29f
RAS: Validate stack pointer after error handling
by Jeenu Viswambharan
· Mon Feb 19 12:25:53 2018 +0000
e86a247
RAS: Move EA handling to a separate file
by Jeenu Viswambharan
· Thu Jul 05 15:24:45 2018 +0100
95f30ab
Add end_vector_entry assembler macro
by Roberto Vargas
· Tue Apr 17 11:31:43 2018 +0100
e834ee1
DynamIQ: Enable MMU without using stack
by Jeenu Viswambharan
· Fri Apr 27 15:17:03 2018 +0100
9a7ce2f
AArch64: Introduce RAS handling
by Jeenu Viswambharan
· Wed Apr 04 16:07:11 2018 +0100
96c7df0
AArch64: Introduce External Abort handling
by Jeenu Viswambharan
· Thu Nov 30 12:54:15 2017 +0000
23d05a8
AArch64: Refactor GP register restore to separate function
by Jeenu Viswambharan
· Wed Nov 29 16:59:34 2017 +0000
35c8cfc
Add support for the SMC Calling Convention 2.0
by Antonio Nino Diaz
· Mon Apr 23 15:43:29 2018 +0100
9c274f8
Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch
by davidcunado-arm
· Wed Feb 28 01:26:21 2018 +0000
7c2a3ca
Add comments about mismatched TCR_ELx and xlat tables
by Antonio Nino Diaz
· Fri Feb 23 15:07:54 2018 +0000
73308d0
Introduce the new BL handover interface
by Soby Mathew
· Tue Jan 09 14:36:14 2018 +0000
e4794b7
Redefine SMC_UNK as -1 instead of 0xFFFFFFFF
by Antonio Nino Diaz
· Wed Feb 14 14:22:29 2018 +0000
0415951
runtime_exceptions: Save x4-x29 unconditionally
by Dimitris Papastamos
· Mon Jan 22 11:53:04 2018 +0000
d79d40d
Merge pull request #1193 from jwerner-chromium/JW_coreboot
by davidcunado-arm
· Wed Jan 24 14:31:53 2018 +0000
446f7f1
Workaround for CVE-2017-5715 on Cortex A57 and A72
by Dimitris Papastamos
· Thu Nov 30 14:53:53 2017 +0000
02eb727
utils_def: Add REGSZ and make BIT() assembly-compatible
by Julius Werner
· Tue Dec 12 14:23:26 2017 -0800
d1a1fd4
Move FPEXC32_EL2 to FP Context
by David Cunado
· Fri Oct 20 11:30:57 2017 +0100
67ebde7
Fix x30 reporting for unhandled exceptions
by Julius Werner
· Thu Jul 27 14:59:34 2017 -0700
fee8653
Fully initialise essential control registers
by David Cunado
· Thu Apr 13 22:38:29 2017 +0100
fa3cf0b
Use SPDX license identifiers
by dp-arm
· Wed May 03 09:38:09 2017 +0100
043fe9c
PSCI: Build option to enable D-Caches early in warmboot
by Soby Mathew
· Mon Apr 10 22:35:42 2017 +0100
d3ec543
Add and use plat_crash_console_flush() API
by Antonio Nino Diaz
· Fri Feb 17 17:11:27 2017 +0000
1fecc8d
Merge pull request #860 from jeenu-arm/hw-asstd-coh
by davidcunado-arm
· Fri Mar 17 12:34:37 2017 +0000
4ef91f1
Simplify translation tables headers dependencies
by Antonio Nino Diaz
· Mon Feb 20 14:22:22 2017 +0000
4614496
Enable data caches early with hardware-assisted coherency
by Jeenu Viswambharan
· Thu Jan 05 10:37:21 2017 +0000
68aef10
Define and use no_ret macro where no return is expected
by Jeenu Viswambharan
· Wed Nov 30 15:21:11 2016 +0000
0980eed
Cosmetic change to exception table
by Douglas Raillard
· Wed Nov 09 17:48:27 2016 +0000
3cac786
Add PMF instrumentation points in TF
by dp-arm
· Mon Sep 19 11:18:44 2016 +0100
d019487
Introduce PSCI Library Interface
by Soby Mathew
· Fri Apr 29 19:01:30 2016 +0100
0d78607
Introduce `el3_runtime` and `PSCI` libraries
by Soby Mathew
· Thu Mar 24 16:56:29 2016 +0000
9e6ad6c
Introduce some helper macros for exception vectors
by Sandrine Bailleux
· Tue May 24 16:56:03 2016 +0100
391a76e
Add 32 bit version of plat_get_syscnt_freq
by Antonio Nino Diaz
· Wed May 18 16:53:31 2016 +0100
2c7ed5b
Dump platform-defined regs in crash reporting
by Gerald Lejeune
· Thu Nov 26 15:47:53 2015 +0100
851dc7e
Add ISR_EL1 to crash report
by Gerald Lejeune
· Tue Mar 22 11:11:46 2016 +0100
632d6df
Enable asynchronous abort exceptions during boot
by Gerald Lejeune
· Tue Mar 22 09:29:23 2016 +0100
1f21bcf
Remove all non-configurable dead loops
by Antonio Nino Diaz
· Mon Feb 01 13:57:25 2016 +0000
f4119ec
Miscellaneous doc fixes for v1.2
by Sandrine Bailleux
· Thu Dec 17 13:58:58 2015 +0000
7d19941
Remove dashes from image names: 'BL3-x' --> 'BL3x'
by Juan Castillo
· Mon Dec 14 09:35:25 2015 +0000
6c0566c
Move context management code to common location
by Yatharth Kochar
· Fri Oct 02 17:56:48 2015 +0100
e77e116
Fix issue in Floating point register restore
by Soby Mathew
· Thu Dec 03 09:42:50 2015 +0000
8f67649
Merge pull request #443 from achingupta/sb/el3_payloads-cb_single_cpu
by danh-arm
· Tue Dec 01 19:02:24 2015 +0000
b21b02f
Introduce COLD_BOOT_SINGLE_CPU build option
by Sandrine Bailleux
· Fri Oct 30 15:05:17 2015 +0000
c5204fa
Remove the IMF_READ_INTERRUPT_ID build option
by Soby Mathew
· Tue Oct 27 10:01:06 2015 +0000
e9c4a64
Make generic code work in presence of system caches
by Achin Gupta
· Fri Sep 11 16:03:13 2015 +0100
3700a92
PSCI: Migrate TF to the new platform API and CM helpers
by Soby Mathew
· Mon Jul 13 11:21:11 2015 +0100
9ccbc03
Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1
by danh-arm
· Wed Jun 24 11:23:33 2015 +0100
449dbd5
Introduce PROGRAMMABLE_RESET_ADDRESS build option
by Sandrine Bailleux
· Tue Jun 02 17:19:43 2015 +0100
acde8b0
Rationalize reset handling code
by Sandrine Bailleux
· Tue May 19 11:54:45 2015 +0100
979992e
Fix handling of spurious interrupts in BL3_1
by Achin Gupta
· Wed May 13 17:57:18 2015 +0100
a877c25
Add support to indicate size and end of assembly functions
by Kévin Petit
· Tue Mar 24 14:03:57 2015 +0000
9b38fc8
Initialise cpu ops after enabling data cache
by Vikram Kanigiri
· Thu Jan 29 18:27:38 2015 +0000
36433d1
Call reset handlers upon BL3-1 entry.
by Yatharth Kochar
· Thu Nov 20 18:09:41 2014 +0000
2ae2043
Remove coherent memory from the BL memory maps
by Soby Mathew
· Thu Jan 08 18:02:44 2015 +0000
046cd3f
Miscellaneous documentation fixes
by Sandrine Bailleux
· Wed Aug 06 11:27:23 2014 +0100
38b4bc9
Add CPU specific crash reporting handlers
by Soby Mathew
· Thu Aug 14 13:36:41 2014 +0100
8e2f287
Add CPU specific power management operations
by Soby Mathew
· Thu Aug 14 12:49:05 2014 +0100
c704cbc
Introduce framework for CPU specific operations
by Soby Mathew
· Thu Aug 14 11:33:56 2014 +0100
ed1744e
Unmask SError interrupt and clear SCR_EL3.EA bit
by Achin Gupta
· Mon Aug 04 23:13:10 2014 +0100
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