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git01.mediatek.com / filogic / atf / 342f4686fde9cc3ba1e9096ec8d76e2683af2afb / lib / cpus / aarch64 / cpu_helpers.S
  1. 667db2c Merge changes from topic "bk/errata_refactor" into integration by Manish Pandey · 1 year, 8 months ago
  2. cc30ccf chore(cpus): remove redundant asserts by Boyan Karatotev · 1 year, 10 months ago
  3. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  4. caa2e05 fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 by Bipin Ravi · 2 years, 9 months ago
  5. 7d0299f fix: random typos in tf-a code base by Olivier Deprez · 3 years, 6 months ago
  6. e1ecd23 arm_fpga: Add support for unknown MPIDs by Javier Almansa Sobrino · 4 years, 3 months ago
  7. 718c876 lib: cpus: sanity check pointers before use by Varun Wadekar · 5 years ago
  8. 94accd3 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · 5 years ago
  9. 4d034c5 Tegra: Support for scatterfile for the BL31 image by Varun Wadekar · 6 years ago
  10. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  11. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · 7 years ago
  12. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · 7 years ago
  13. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · 7 years ago
  14. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · 7 years ago
  15. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · 7 years ago
  16. 815faa8 Use a callee-saved register to be AAPCS-compliant by dp-arm · 8 years ago
  17. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  18. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · 8 years ago
  19. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · 8 years ago
  20. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · 8 years ago
  21. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · 8 years ago
  22. 1f5f812 Correct system include order by David Cunado · 8 years ago
  23. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · 8 years ago
  24. 6b28c57 Make cpu operations warning a VERBOSE print by Soby Mathew · 9 years ago
  25. d481759 Disable non-temporal hint on Cortex-A53/57 by Sandrine Bailleux · 9 years ago
  26. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · 10 years ago
  27. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · 10 years ago
  28. b5a6304 Fix the Cortex-A57 reset handler register usage by Soby Mathew · 10 years ago
  29. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 10 years ago
  30. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · 10 years ago
  31. c088433 Apply errata workarounds only when major/minor revisions match. by Soby Mathew · 10 years ago
  32. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · 10 years ago
  33. 8e2f287 Add CPU specific power management operations by Soby Mathew · 10 years ago
  34. f1785fd Add platform API for reset handling by Soby Mathew · 10 years ago
  35. c704cbc Introduce framework for CPU specific operations by Soby Mathew · 10 years ago