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git01.mediatek.com / filogic / atf / 2f4cc717bac4401a0a58839ddb1e1ab08e66e44d / plat / xilinx / versal / include / versal_def.h
  1. 2f4cc71 xilinx: versal: Wire silicon default setup by Siva Durga Prasad Paladugu · 5 years ago
  2. 41dd096 plat: xilinx: versal: Dont set IOU switch clock by Siva Durga Prasad Paladugu · 5 years ago
  3. 10161e5 arm64: versal: Adjust cpu clock for versal virtual by Siva Durga Prasad Paladugu · 5 years ago
  4. 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · 5 years ago
  5. fe0e10a xilinx: versal: Add support for suspend related APIs by Tejas Patel · 4 years, 7 months ago
  6. 354fe57 xilinx: Add support to send PM API to PMC using IPI for versal by Tejas Patel · 6 years ago
  7. 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · 6 years ago[Renamed (97%) from plat/xilinx/versal/versal_def.h]
  8. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  9. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · 6 years ago