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git01.mediatek.com / filogic / atf / 2f38ce3d95af4d18a167157be3e0704d3742ce7d / plat / nvidia / tegra / soc
  1. 8b82fae Tegra: introduce per-soc system reset handler by Varun Wadekar · 9 years ago
  2. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  3. e98a146 Tegra132: set TZDRAM_BASE to 0xF5C00000 by Varun Wadekar · 9 years ago
  4. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · 9 years ago
  5. 0f3baa0 Tegra: Support for Tegra's T132 platforms by Varun Wadekar · 9 years ago
  6. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · 9 years ago
  7. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  8. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  9. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · 9 years ago
  10. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · 9 years ago
  11. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · 9 years ago
  12. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 10 years ago