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git01.mediatek.com / filogic / atf / 2bb78d3ab2ae07aa94a6eaa6587861eb7da538c3 / plat / xilinx / zynqmp / include
  1. efd431b zynqmp: Add wdt timeout restart functionality by Siva Durga Prasad Paladugu · Mon Apr 30 20:12:12 2018 +0530
  2. 8f5ddb3 zynqmp: Use DDR memory when DEBUG is enabled by Jolly Shah · Tue Jan 30 11:31:53 2018 -0800
  3. c150312 Update ULL() macro and instances of ull to comply with MISRA by David Cunado · Fri Feb 16 21:12:58 2018 +0000
  4. 9bde130 zynqmp: Migrate to using interrupt properties by Jeenu Viswambharan · Fri Sep 29 11:15:18 2017 +0100
  5. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  6. 6a9e03e zynqmp: Migrate to new address space macros by Soren Brinkmann · Fri Jan 06 11:07:00 2017 -0800
  7. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · Wed Nov 16 15:50:14 2016 -0800
  8. 7ac746c zynqmp: Increase MAX_XLAT_TABLES by Soren Brinkmann · Mon Jul 25 10:33:53 2016 -0700
  9. 802ba1d zynqmp: Change default BL31 address space by Soren Brinkmann · Fri Jul 15 06:23:37 2016 -0700
  10. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · Fri Jul 08 14:45:14 2016 -0700
  11. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · Fri Apr 22 10:02:46 2016 -0700
  12. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · Thu Apr 14 10:27:00 2016 -0700
  13. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · Thu Nov 26 15:47:53 2015 +0100
  14. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800