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git01.mediatek.com / filogic / atf / 2bb78d3ab2ae07aa94a6eaa6587861eb7da538c3 / include / common
  1. 9fe8804 Allow disabling authentication dynamically by Soby Mathew · Mon Mar 26 12:43:37 2018 +0100
  2. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · Wed Apr 04 16:07:11 2018 +0100
  3. 35c8cfc Add support for the SMC Calling Convention 2.0 by Antonio Nino Diaz · Mon Apr 23 15:43:29 2018 +0100
  4. 09f51d4 Merge pull request #1357 from antonio-nino-diaz-arm/an/fix-misra by Dimitris Papastamos · Wed Apr 18 10:54:26 2018 +0100
  5. e881147 Fix some MISRA defects in SPM code by Antonio Nino Diaz · Tue Apr 17 15:10:18 2018 +0100
  6. b72de19 Merge pull request #1356 from robertovargas-arm/misra-changes by Dimitris Papastamos · Mon Apr 16 15:04:28 2018 +0100
  7. be126ed Fix MISRA rule 8.3 Part 4 by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  8. 54f5d67 fix instruction address range limitation by Jiafei Pan · Tue Mar 27 23:00:55 2018 +0800
  9. 43a7bf4 Add support for BL2 in XIP memory by Jiafei Pan · Wed Mar 21 07:20:09 2018 +0000
  10. 5cc3bc8 Clean usage of void pointers to access symbols by Joel Hutton · Wed Mar 21 11:40:57 2018 +0000
  11. 3c817f4 Rename 'smcc' to 'smccc' by Antonio Nino Diaz · Wed Mar 21 10:49:27 2018 +0000
  12. 2ca18d9 Fix MISRA rule 8.4 Part 1 by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  13. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  14. 777dd43 Fix MISRA rule 8.3 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  15. cc36484 Dynamic cfg: MISRA fixes by Soby Mathew · Wed Feb 21 01:16:39 2018 +0000
  16. 96a1c6b ARM Platforms: Load HW_CONFIG in BL2 by Soby Mathew · Mon Jan 15 14:45:33 2018 +0000
  17. b9fccca Dynamic cfg: Introduce fdt wrappers by Soby Mathew · Mon Nov 06 13:56:40 2017 +0000
  18. 40eb4b6 Add dynamic config image IDs by Soby Mathew · Mon Jan 08 13:36:49 2018 +0000
  19. 0bdfef0 Dynamic cfg: Add HW and TB_FW configs to CoT by Soby Mathew · Tue Nov 07 17:03:57 2017 +0000
  20. 7814a95 Merge pull request #1173 from etienne-lms/armv7-qemu by davidcunado-arm · Wed Feb 07 11:57:19 2018 +0800
  21. 094041d aarch32: use lr as bl32 boot argument on aarch32 only systems by Etienne Carriere · Fri Feb 02 13:16:18 2018 +0100
  22. 18f65db image_decompress: add APIs for decompressing images by Masahiro Yamada · Fri Jan 26 11:42:01 2018 +0900
  23. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  24. d79d40d Merge pull request #1193 from jwerner-chromium/JW_coreboot by davidcunado-arm · Wed Jan 24 14:31:53 2018 +0000
  25. b5d1f8e Merge pull request #1200 from robertovargas-arm/bl2-el3 by davidcunado-arm · Fri Jan 19 13:40:12 2018 +0000
  26. 0a4cded sp_min: Implement workaround for CVE-2017-5715 by Dimitris Papastamos · Tue Jan 02 11:37:02 2018 +0000
  27. e4e342d Mark functions defined in assembly files by Roberto Vargas · Thu Nov 02 16:36:51 2017 +0000
  28. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  29. 446f7f1 Workaround for CVE-2017-5715 on Cortex A57 and A72 by Dimitris Papastamos · Thu Nov 30 14:53:53 2017 +0000
  30. 94f8907 Add new function-pointer-based console API by Julius Werner · Mon Jul 31 18:15:11 2017 -0700
  31. 4213a3f Merge pull request #1178 from davidcunado-arm/dc/enable_sve by davidcunado-arm · Mon Dec 11 12:29:47 2017 +0000
  32. 7c8af06 Unify cache flush code path after image load by Soby Mathew · Fri Nov 10 13:14:40 2017 +0000
  33. ce88eee Enable SVE for Non-secure world by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  34. 42ef554 Merge pull request #1145 from etienne-lms/rfc-armv7-2 by davidcunado-arm · Thu Nov 23 23:41:24 2017 +0000
  35. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
  36. c41f206 SPM: Introduce Secure Partition Manager by Antonio Nino Diaz · Tue Oct 24 10:07:35 2017 +0100
  37. 4cce835 ARMv7 may not support Virtualization Extensions by Etienne Carriere · Wed Nov 08 14:38:33 2017 +0100
  38. 863858b ARMv7 does not support SDCR by Etienne Carriere · Sun Nov 05 22:55:55 2017 +0100
  39. 70b1c2f ARMv7 does not support STL instruction by Etienne Carriere · Sun Nov 05 22:55:47 2017 +0100
  40. aeb267c GIC: Allow specifying interrupt properties by Jeenu Viswambharan · Fri Sep 22 08:32:09 2017 +0100
  41. aaf15f5 Implement log framework by Soby Mathew · Mon Sep 04 11:49:29 2017 +0100
  42. f583a06 Introduce tf_vprintf() and tf_string_print() by Soby Mathew · Mon Sep 04 11:45:52 2017 +0100
  43. e94b06d Merge pull request #1078 from douglas-raillard-arm/dr/add_cfi_vector_entry by davidcunado-arm · Thu Sep 07 00:45:59 2017 +0100
  44. 878f03c Merge pull request #1019 from etienne-lms/log-size by davidcunado-arm · Thu Sep 07 00:40:59 2017 +0100
  45. 97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
  46. efa50b5 Add CFI debug info to vector entries by Douglas Raillard · Mon Aug 07 16:20:46 2017 +0100
  47. be1d3ef asm_macros: set the default assembly code alignment to 4 byte by Masahiro Yamada · Thu Aug 31 14:29:34 2017 +0900
  48. b4c75e9 Add new alignment parameter to func assembler macro by Julius Werner · Tue Aug 01 15:16:36 2017 -0700
  49. 8072678 Support Trusted OS firmware extra images in TF tools by Summer Qin · Thu Apr 20 16:28:39 2017 +0100
  50. ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
  51. fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
  52. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  53. 34e7843 Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memory by davidcunado-arm · Tue May 30 10:56:47 2017 +0100
  54. 9c107fa Introduce `tf_snprintf` by Antonio Nino Diaz · Wed May 17 15:34:22 2017 +0100
  55. e3a2b31 fip: move headers shared between TF and fiptool to include/tools_share by Masahiro Yamada · Mon May 08 18:29:03 2017 +0900
  56. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  57. 7d99b6c Merge branch 'integration' into tf_issue_461 by Scott Branden · Sat Apr 29 08:36:12 2017 -0700
  58. bf404c0 Move defines in utils.h to utils_def.h to fix shared header compile issues by Scott Branden · Mon Apr 10 11:45:52 2017 -0700
  59. bf360df Merge pull request #910 from dp-arm/dp/AArch32-juno-port by davidcunado-arm · Fri Apr 21 17:10:27 2017 +0100
  60. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  61. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · Thu Apr 20 09:58:28 2017 +0100
  62. 18e6004 Merge pull request #886 from dp-arm/dp/stack-protector by davidcunado-arm · Thu Apr 06 10:20:47 2017 +0100
  63. 306593d Add support for GCC stack protection by Douglas Raillard · Fri Feb 24 18:14:15 2017 +0000
  64. b911cc7 Re-factor header files for easier PSCI library integration by Soby Mathew · Mon Feb 13 12:46:28 2017 +0000
  65. 88de358 Merge pull request #841 from dp-arm/dp/debug-regs by danh-arm · Mon Feb 20 13:58:48 2017 +0000
  66. 595d0d5 Disable secure self-hosted debug via MDCR_EL3/SDCR by dp-arm · Wed Feb 08 11:51:50 2017 +0000
  67. 21362a9 Introduce unified API to zero memory by Douglas Raillard · Fri Dec 02 13:51:54 2016 +0000
  68. 54ec86a Allow spin locks to be defined from assembly by Jeenu Viswambharan · Thu Jan 19 14:23:36 2017 +0000
  69. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  70. 2b7d7ae Merge pull request #791 from jeenu-arm/asm-assert-32 by danh-arm · Tue Dec 20 17:00:32 2016 +0000
  71. b0e529b Export is_mem_free() function by Sandrine Bailleux · Tue Nov 08 14:27:10 2016 +0000
  72. ff640c4 AArch32: Print ASM_ASSERT and panic messages by Jeenu Viswambharan · Mon Nov 28 09:59:27 2016 +0000
  73. 975d08c Merge pull request #774 from jeenu-arm/no-return-macro by danh-arm · Mon Dec 12 14:29:01 2016 +0000
  74. 68aef10 Define and use no_ret macro where no return is expected by Jeenu Viswambharan · Wed Nov 30 15:21:11 2016 +0000
  75. c14b08e Reset EL2 and EL3 configurable controls by David Cunado · Fri Nov 25 00:21:59 2016 +0000
  76. 1c0e208 Add CFI debug frame information for ASM functions by Douglas Raillard · Mon Nov 21 14:12:32 2016 +0000
  77. 5f55e28 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR by David Cunado · Mon Oct 31 17:37:34 2016 +0000
  78. c44c5af AArch32: Add `memcpy4` function in assembly by Yatharth Kochar · Wed Sep 28 11:00:05 2016 +0100
  79. 89256b8 PSCI: Introduce PSCI Library argument structure by Soby Mathew · Tue Sep 13 14:19:08 2016 +0100
  80. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · Tue Jun 28 16:58:26 2016 +0100
  81. 3345a8d Add new version of image loading. by Yatharth Kochar · Mon Sep 12 16:08:41 2016 +0100
  82. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  83. a9482df AArch32: Add API to invoke runtime service handler by Soby Mathew · Thu May 05 12:49:09 2016 +0100
  84. d29f67b AArch32: Add assembly helpers by Soby Mathew · Thu May 05 12:31:57 2016 +0100
  85. b9ff2fd Rearrange assembly helper macros by Soby Mathew · Fri Jul 08 15:26:35 2016 +0100
  86. d019487 Introduce PSCI Library Interface by Soby Mathew · Fri Apr 29 19:01:30 2016 +0100
  87. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000
  88. 24ab34f Fix coding guideline warnings by Soby Mathew · Tue May 03 17:11:42 2016 +0100
  89. a0fedc4 Rework type usage in Trusted Firmware by Soby Mathew · Thu Jun 16 14:52:04 2016 +0100
  90. ba39fc6 Merge pull request #662 from sandrine-bailleux-arm/sb/rodata-xn by danh-arm · Fri Jul 15 18:55:43 2016 +0100
  91. f91f144 Introduce SEPARATE_CODE_AND_RODATA build flag by Sandrine Bailleux · Fri Jul 08 14:37:40 2016 +0100
  92. 7659a26 Introduce utils.h header file by Sandrine Bailleux · Tue Jul 05 09:55:03 2016 +0100
  93. bfdbecf Derive stack alignment from CACHE_WRITEBACK_GRANULE by Soby Mathew · Thu Jun 09 17:16:35 2016 +0100
  94. a913dee Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs by danh-arm · Fri Jun 03 15:12:37 2016 +0100
  95. d75d2ba Build option to include AArch32 registers in cpu context by Soby Mathew · Tue May 17 14:01:32 2016 +0100
  96. 618ba99 Fill exception vectors with zero bytes by Sandrine Bailleux · Tue May 24 16:22:59 2016 +0100
  97. 9e6ad6c Introduce some helper macros for exception vectors by Sandrine Bailleux · Tue May 24 16:56:03 2016 +0100
  98. 37a12df Fix build error with optimizations disabled (-O0) by Sandrine Bailleux · Mon Apr 11 13:17:50 2016 +0100
  99. 074e05a Enable SCR_EL3.SIF bit by Soby Mathew · Mon Apr 04 12:34:24 2016 +0100
  100. 632d6df Enable asynchronous abort exceptions during boot by Gerald Lejeune · Tue Mar 22 09:29:23 2016 +0100