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filogic
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atf
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2b0a176d5918ff8ec25308fe83a317eea0cf92b3
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lib
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cpus
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aarch64
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cpu_helpers.S
ee5eb80
Add provision to extend CPU operations at more levels
by Jeenu Viswambharan
· Fri Nov 18 12:58:28 2016 +0000
6b28c57
Make cpu operations warning a VERBOSE print
by Soby Mathew
· Mon Mar 21 10:36:47 2016 +0000
d481759
Disable non-temporal hint on Cortex-A53/57
by Sandrine Bailleux
· Wed Jan 13 14:57:38 2016 +0000
a877c25
Add support to indicate size and end of assembly functions
by Kévin Petit
· Tue Mar 24 14:03:57 2015 +0000
9b38fc8
Initialise cpu ops after enabling data cache
by Vikram Kanigiri
· Thu Jan 29 18:27:38 2015 +0000
b5a6304
Fix the Cortex-A57 reset handler register usage
by Soby Mathew
· Thu Jan 29 12:00:58 2015 +0000
36433d1
Call reset handlers upon BL3-1 entry.
by Yatharth Kochar
· Thu Nov 20 18:09:41 2014 +0000
7d861ea
Invalidate the dcache after initializing cpu-ops
by Soby Mathew
· Tue Nov 18 10:14:14 2014 +0000
c088433
Apply errata workarounds only when major/minor revisions match.
by Soby Mathew
· Mon Sep 22 12:11:36 2014 +0100
38b4bc9
Add CPU specific crash reporting handlers
by Soby Mathew
· Thu Aug 14 13:36:41 2014 +0100
8e2f287
Add CPU specific power management operations
by Soby Mathew
· Thu Aug 14 12:49:05 2014 +0100
f1785fd
Add platform API for reset handling
by Soby Mathew
· Thu Aug 14 12:22:32 2014 +0100
c704cbc
Introduce framework for CPU specific operations
by Soby Mathew
· Thu Aug 14 11:33:56 2014 +0100