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git01.mediatek.com / filogic / atf / 2967bf4995b816a980396623ffb7cb55da18c06a / plat / rockchip / rk3399 / drivers / pmu / m0_ctl.c
  1. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · 7 years ago
  2. e363146 Fix order of remaining platform #includes by Isla Mitchell · 7 years ago
  3. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  4. 22a9871 rockchip: rk3399: Clean up and seprate secure parts from SoC codes by Xing Zheng · 8 years ago
  5. 8140b7d rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error by Lin Huang · 8 years ago
  6. 61230b0 FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init by Xing Zheng · 8 years ago
  7. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · 8 years ago
  8. c8e5c78 rockchip: rk3399: fix hang in ddr set rate by Derek Basehore · 8 years ago
  9. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · 8 years ago