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git01.mediatek.com / filogic / atf / 28f69abf4e4d6e61eca8094ef3309f7ff0af9946 / plat / nvidia / tegra / soc / t210 / platform_t210.mk
  1. 1108fc6 plat/tegra: Enable Cortex-A53 erratum 855873 workaround by Andre Przywara · 8 years ago
  2. ed3c62b Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs by Varun Wadekar · 7 years ago
  3. 1edb882 Tegra210: new TZDRAM base address by Varun Wadekar · 8 years ago
  4. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · 9 years ago
  5. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · 9 years ago
  6. 7a9a285 Tegra: Memory Controller Driver (v1) by Varun Wadekar · 9 years ago
  7. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  8. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · 9 years ago
  9. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · 9 years ago
  10. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · 9 years ago
  11. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  12. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  13. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  14. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago