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git01.mediatek.com / filogic / atf / 26c10678e381b57b196343cb8664483c2b120303 / plat / nvidia / tegra / soc / t210 / drivers / se
  1. 45ad08b Tegra210: SE: switch SE clock source to CLK_M by Leo He · Thu Jul 12 17:36:12 2018 +0800
  2. 1dbd19c Tegra210: SE: add context save support by Harvey Hsieh · Tue Apr 10 18:16:51 2018 +0800
  3. 5ac897f plat: nvidia: remove spurious UTF-8 characters at top of platform files by Olivier Deprez · Thu Jan 09 10:45:52 2020 +0100
  4. ffbf32a Makefile: remove extra include paths in INCLUDES by Ambroise Vincent · Thu Mar 28 09:01:18 2019 +0000
  5. 69b0e4a Tegra210_B01: SC7: Select RNG mode based on ECID by Samuel Payne · Thu Jun 15 21:12:45 2017 -0700
  6. 40d3a67 Tegra210B01: SE/SE2 and PKA1 context save (SW) by Marvin Hsu · Tue Apr 11 11:00:48 2017 +0800
  7. 0e07e45 Tegra: fix defects flagged by MISRA Rule 10.3 by Anthony Zhou · Wed Jul 26 17:16:54 2017 +0800
  8. 1e6bed4 Tegra210: se: enable entropy/SE clocks before system suspend by Samuel Payne · Mon Jun 12 10:15:43 2017 -0700
  9. ae1e079 Tegra210: se: disable SMMU before suspending SE block by Samuel Payne · Mon Jun 12 16:38:23 2017 -0700
  10. 25fdca2 Tegra210: SE: remove logic to enable atomic save/restore by Samuel Payne · Thu Jun 15 13:57:47 2017 -0700
  11. 809c773 Tegra210B01: initialize DRBG on boot and resume by Sam Payne · Mon May 15 11:10:37 2017 -0700
  12. 21eea97 Tegra210B01: SE1 and SE2/PKA1 context save (atomic) by Marvin Hsu · Tue Apr 11 11:00:48 2017 +0800