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git01.mediatek.com / filogic / atf / 2694cba64ea1d6b7797c9b1fd4f792b35b70bfac / plat / rockchip / rk3399 / drivers / pmu / m0_ctl.h
  1. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · Mon Dec 12 15:18:08 2016 +0800
  2. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · Wed Oct 26 21:25:26 2016 +0800[Renamed (83%) from plat/rockchip/rk3399/drivers/pmu/rk3399m0.h]
  3. b400374 rockchip: add M0 source code and build system for RK3399 by Caesar Wang · Wed Oct 12 08:10:12 2016 +0800