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git01.mediatek.com / filogic / atf / 259fffe28239dbaae63946ab815b2b349614d6e0 / plat / intel / soc / agilex / bl31_plat_setup.c
  1. 2be03c0 fix(tree): correct some typos by Elyes Haouas · Mon Feb 13 09:14:48 2023 +0100
  2. bd8da63 feat(intel): extending to support SMMU in FCS by Sieu Mun Tang · Wed Sep 28 15:58:28 2022 +0800
  3. 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:40:46 2020 +0800
  4. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · Fri Aug 06 01:16:46 2021 +0800
  5. 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · Mon May 11 00:55:01 2020 +0800
  6. 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · Fri Apr 24 21:51:00 2020 +0800
  7. 98b5a11 16550: Use generic console_t data structure by Andre Przywara · Sat Jan 25 00:58:35 2020 +0000
  8. 593c4c5 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · Tue Dec 17 19:22:17 2019 +0800
  9. 218d8fe intel: agilex: Enable uboot BL31 loading by Hadi Asyrafi · Tue Jan 14 10:51:31 2020 +0800
  10. 5ae876f intel: Refactor common platform code [5/5] by Hadi Asyrafi · Wed Oct 23 17:58:06 2019 +0800
  11. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · Wed Oct 23 16:26:53 2019 +0800
  12. e944d22 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · Tue Jul 30 10:56:38 2019 +0800
  13. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · Thu Jun 27 11:34:03 2019 +0800