1. 919d3c8 refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only by Boyan Karatotev · Mon Feb 13 16:32:47 2023 +0000
  2. 1e966f3 refactor(amu): separate the EL2 and EL3 enablement code by Boyan Karatotev · Mon Mar 27 17:02:43 2023 +0100
  3. 6468d4a refactor(cpufeat): separate the EL2 and EL3 enablement code by Boyan Karatotev · Thu Feb 16 15:12:45 2023 +0000
  4. 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · Wed Feb 15 13:21:50 2023 +0000
  5. d62c681 feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED by Jayanth Dodderi Chidanand · Tue Mar 07 10:43:19 2023 +0000
  6. 605419a feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED by Jayanth Dodderi Chidanand · Mon Mar 06 23:56:14 2023 +0000
  7. 906776e refactor(amu): use new AMU feature check routines by Andre Przywara · Fri Mar 03 10:30:06 2023 +0000
  8. 44e33e0 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  9. a1c9ad1 fix(cpufeat): make stub enable functions "static inline" by Andre Przywara · Wed Mar 22 13:25:00 2023 +0000
  10. 84b8653 refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  11. f3e8cfc refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  12. 77b8b87 fix(cpufeat): resolve build errors due to compiler optimization by Jayanth Dodderi Chidanand · Wed Mar 01 15:35:28 2023 +0000
  13. 8186596 feat(brbe): add BRBE support for NS world by johpow01 · Fri Jan 28 17:06:20 2022 -0600
  14. 4b5489c refactor(twed): improve TWED enablement in EL-3 by Jayanth Dodderi Chidanand · Mon Mar 28 15:28:55 2022 +0100
  15. 9baade3 feat(sme): enable SME functionality by johpow01 · Thu Jul 08 14:14:00 2021 -0500
  16. f11909f feat(amu): enable per-core AMU auxiliary counters by Chris Kay · Thu Aug 19 11:21:52 2021 +0100
  17. 26a7961 refactor(amu): refactor enablement and context switching by Chris Kay · Mon May 24 20:35:26 2021 +0100
  18. da81914 refactor(amu): detect auxiliary counters at runtime by Chris Kay · Tue May 25 15:24:18 2021 +0100
  19. a40141d refactor(amu): detect architected counters at runtime by Chris Kay · Tue May 25 12:33:18 2021 +0100
  20. 925fda4 refactor(amu): conditionally compile auxiliary counter support by Chris Kay · Tue May 25 10:42:56 2021 +0100
  21. f13c6b5 refactor(amu)!: privatize unused AMU APIs by Chris Kay · Mon May 24 21:00:07 2021 +0100
  22. f8ba62b refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK` by Chris Kay · Mon May 17 14:47:25 2021 +0100
  23. 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · Thu Jul 08 09:33:18 2021 +0100
  24. f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · Tue Jun 29 11:44:20 2021 +0100
  25. 20df29c feat(trbe): enable access to trace buffer control registers from lower NS EL by Manish V Badarkhe · Fri Jul 02 09:10:56 2021 +0100
  26. cac7d16 fix(el3_runtime): fix SVE and AMU extension enablement flags by Arunachalam Ganapathy · Thu Jul 08 09:35:57 2021 +0100
  27. 5e37166 refactor(mpam): remove unused function declaration by Manish V Badarkhe · Fri Jul 09 14:30:29 2021 +0100
  28. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
  29. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · Fri Oct 02 13:41:11 2020 -0500
  30. 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · Tue Jul 14 08:17:56 2020 +0100
  31. 70f6597 Tegra194: add RAS exception handling by David Pu · Mon Mar 18 15:14:49 2019 -0700
  32. 3e24c16 Enable v8.6 WFE trap delays by johpow01 · Wed Apr 22 14:05:13 2020 -0500
  33. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  34. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  35. 56b68ad Minor changes to documentation and comments by Antonio Nino Diaz · Thu Feb 28 13:35:21 2019 +0000
  36. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  37. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  38. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  39. 4b32e62 libc: Fix all includes in codebase by Antonio Nino Diaz · Thu Aug 16 16:52:57 2018 +0100
  40. 69ac42b Merge pull request #1532 from jeenu-arm/misra-fixes by Dimitris Papastamos · Wed Aug 22 10:25:41 2018 +0100
  41. 31ac01e RAS: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  42. 2da918c AArch64: Enable MPAM for lower ELs by Jeenu Viswambharan · Tue Jul 31 16:13:33 2018 +0100
  43. 9d4c9c1 RAS: Introduce handler for Uncontainable errors by Jeenu Viswambharan · Thu May 17 09:52:36 2018 +0100
  44. d86cc5b RAS: Allow individual interrupt registration by Jeenu Viswambharan · Tue Dec 12 10:34:58 2017 +0000
  45. 2e2e881 RAS: Add support for node registration by Jeenu Viswambharan · Fri Dec 08 15:38:21 2017 +0000
  46. 19f6cf2 RAS: Add helpers to access Standard Error Records by Jeenu Viswambharan · Thu Dec 07 08:43:05 2017 +0000
  47. 5e8cd79 Implement {spe,sve}_supported() helpers and refactor code by Dimitris Papastamos · Mon Feb 19 14:52:19 2018 +0000
  48. 0dcdd8d AMU: Implement context save/restore for aarch32 by Joel Hutton · Thu Dec 21 15:21:20 2017 +0000
  49. 525c37a AMU: Add configuration helpers for aarch64 by Dimitris Papastamos · Mon Nov 13 09:49:45 2017 +0000
  50. 60346db AMU: Add plat interface to select which group 1 counters to enable by Dimitris Papastamos · Wed Dec 13 10:54:37 2017 +0000
  51. ce88eee Enable SVE for Non-secure world by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  52. e08005a AMU: Implement support for aarch64 by Dimitris Papastamos · Thu Oct 12 13:02:29 2017 +0100
  53. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100