Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
atf
/
1ed3ad55e2268f9415328c4d4cc634d4ed4b265c
/
lib
/
cpus
/
aarch64
/
cortex_a53.S
f4acb92
ti: k3: common: Remove coherency workaround for AM65x
by Andrew F. Davis
· 5 years ago
3e2ef2e
Cortex-A53: Fix reporting of missing errata when not needed
by Andrew F. Davis
· 5 years ago
f5fdfbc
Cortex-A53: Workarounds for 819472, 824069 and 827319
by Ambroise Vincent
· 6 years ago
e0f9063
Sanitise includes across codebase
by Antonio Nino Diaz
· 6 years ago
7c461d7
ti: k3: common: Do not disable cache on TI K3 core powerdown
by Andrew F. Davis
· 6 years ago
6e1796e
Check presence of fix for errata 835769 in Cortex-A53
by Jonathan Wright
· 6 years ago
efb1f33
Check presence of fix for errata 843419 in Cortex-A53
by Jonathan Wright
· 6 years ago
41b61be
CPU: Correct names of implementation-defined aux regs
by Eleanor Bonnici
· 7 years ago
d56fb04
Apply workarounds for A53 Cat A Errata 835769 and 843419
by Douglas Raillard
· 7 years ago
1384a16
Unique names for defines in the CPU libraries
by Varun Wadekar
· 7 years ago
fa3cf0b
Use SPDX license identifiers
by dp-arm
· 7 years ago
00eefd9
Add workaround for ARM Cortex-A53 erratum 855873
by Andre Przywara
· 8 years ago
d5ec367
Report errata workaround status to console
by Jeenu Viswambharan
· 8 years ago
ee5eb80
Add provision to extend CPU operations at more levels
by Jeenu Viswambharan
· 8 years ago
6a72a91
bl31: Add error reporting registers
by Naga Sureshkumar Relli
· 8 years ago
6b28c57
Make cpu operations warning a VERBOSE print
by Soby Mathew
· 9 years ago
f12a31d
Cortex-Axx: Unconditionally apply CPU reset operations
by Sandrine Bailleux
· 9 years ago
d481759
Disable non-temporal hint on Cortex-A53/57
by Sandrine Bailleux
· 9 years ago
4fceaca
cortex_a53: Add A53 errata #826319, #836870
by developer
· 9 years ago
a877c25
Add support to indicate size and end of assembly functions
by Kévin Petit
· 9 years ago
b5a6304
Fix the Cortex-A57 reset handler register usage
by Soby Mathew
· 10 years ago
36433d1
Call reset handlers upon BL3-1 entry.
by Yatharth Kochar
· 10 years ago
42aa5eb
Add support for level specific cache maintenance operations
by Soby Mathew
· 10 years ago
38b4bc9
Add CPU specific crash reporting handlers
by Soby Mathew
· 10 years ago
8e2f287
Add CPU specific power management operations
by Soby Mathew
· 10 years ago
c704cbc
Introduce framework for CPU specific operations
by Soby Mathew
· 10 years ago
[Copied (82%) from lib/aarch64/cpu_helpers.S]
c61399b
Merge pull request #191 from danh-arm/jc/tf-issues/218
by danh-arm
· 10 years ago