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git01.mediatek.com / filogic / atf / 1afdfb030295a8449418452bc9e5a15a22bb84f3 / lib / el3_runtime
  1. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  2. 830f0ad Enable MTE support unilaterally for Normal World by Soby Mathew · Fri Jul 12 09:23:38 2019 +0100
  3. b5cf10f Fix restoring APIBKey registers by Sandrine Bailleux · Thu Mar 14 11:38:01 2019 +0100
  4. 899146b Merge pull request #1848 from antonio-nino-diaz-arm/an/docs by Antonio Niño Díaz · Fri Mar 01 09:16:58 2019 +0000
  5. 56b68ad Minor changes to documentation and comments by Antonio Nino Diaz · Thu Feb 28 13:35:21 2019 +0000
  6. 23b7b69 Merge pull request #1839 from loumay-arm/lm/a7x_errata by Antonio Niño Díaz · Thu Feb 28 10:19:24 2019 +0000
  7. 25cda67 Add support for pointer authentication by Antonio Nino Diaz · Tue Feb 19 11:53:51 2019 +0000
  8. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
  9. 13adfb1 Cleanup context handling library by Antonio Nino Diaz · Wed Jan 30 20:41:31 2019 +0000
  10. 78a0aed Add workaround for errata 764081 of Cortex-A75 by Louis Mayencourt · Wed Feb 20 12:11:41 2019 +0000
  11. 1fbc97b Correct typographical errors by Paul Beesley · Fri Jan 11 18:26:51 2019 +0000
  12. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  13. 864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
  14. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  15. cbad661 AArch64: Enable lower ELs to use pointer authentication by Jeenu Viswambharan · Wed Aug 15 14:29:29 2018 +0100
  16. 5753e49 Mark BL31 initialization functions by Daniel Boulby · Thu Sep 20 14:12:46 2018 +0100
  17. c51a2ec context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation by Julius Werner · Tue Aug 28 14:45:43 2018 -0700
  18. 2da918c AArch64: Enable MPAM for lower ELs by Jeenu Viswambharan · Tue Jul 31 16:13:33 2018 +0100
  19. fe5c421 Merge pull request #1392 from dp-arm/dp/cve_2018_3639 by Dimitris Papastamos · Tue May 29 09:28:05 2018 +0100
  20. 28dce9e context_mgmt: Make cm_init_context_common public by Antonio Nino Diaz · Tue May 22 10:09:10 2018 +0100
  21. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  22. b2f1003 Merge pull request #1376 from vwadekar/cm-init-actlr-el1 by Dimitris Papastamos · Tue May 15 18:40:46 2018 +0100
  23. b6dd0b3 lib: el3_runtime: initialise actlr_el1 to hardware defaults by Varun Wadekar · Tue May 08 10:52:36 2018 -0700
  24. f00da74 RAS: Add fault injection support by Jeenu Viswambharan · Fri Dec 08 12:13:51 2017 +0000
  25. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · Wed Apr 04 16:07:11 2018 +0100
  26. 23d05a8 AArch64: Refactor GP register restore to separate function by Jeenu Viswambharan · Wed Nov 29 16:59:34 2017 +0000
  27. 3c817f4 Rename 'smcc' to 'smccc' by Antonio Nino Diaz · Wed Mar 21 10:49:27 2018 +0000
  28. ce88eee Enable SVE for Non-secure world by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  29. dda48b0 AMU: Implement support for aarch32 by Dimitris Papastamos · Tue Oct 17 14:03:14 2017 +0100
  30. e08005a AMU: Implement support for aarch64 by Dimitris Papastamos · Thu Oct 12 13:02:29 2017 +0100
  31. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
  32. 1e6f93e Factor out extension enabling to a separate function by Dimitris Papastamos · Tue Nov 07 09:55:29 2017 +0000
  33. d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  34. a7921b9 aarch64: Add PubSub events to capture security state transitions by Dimitris Papastamos · Fri Oct 13 15:27:58 2017 +0100
  35. 4168f2f Init and save / restore of PMCR_EL0 / PMCR by David Cunado · Mon Oct 02 17:41:39 2017 +0100
  36. 878f03c Merge pull request #1019 from etienne-lms/log-size by davidcunado-arm · Thu Sep 07 00:40:59 2017 +0100
  37. 97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
  38. 00eac15 fix a typo about sctlr_el2 by Ken Kuang · Wed Aug 23 16:03:29 2017 +0800
  39. ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
  40. fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
  41. 6715485 Merge pull request #927 from jeenu-arm/state-switch by davidcunado-arm · Thu May 11 16:04:52 2017 +0100
  42. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  43. 2a9b882 Add macro to check whether the CPU implements an EL by Jeenu Viswambharan · Tue Feb 21 14:40:44 2017 +0000
  44. a8954fc Replace some memset call by zeromem by Douglas Raillard · Thu Jan 26 15:54:44 2017 +0000
  45. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  46. adb7027 AArch32: Fix the stack alignment issue by Soby Mathew · Tue Dec 06 12:10:51 2016 +0000
  47. c14b08e Reset EL2 and EL3 configurable controls by David Cunado · Fri Nov 25 00:21:59 2016 +0000
  48. 5f55e28 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR by David Cunado · Mon Oct 31 17:37:34 2016 +0000
  49. a993c42 Unify SCTLR initialization for AArch32 normal world by Soby Mathew · Thu Sep 29 14:15:57 2016 +0100
  50. b4a970a AArch32: Fix SCTLR context initialization by Soby Mathew · Wed Aug 31 12:34:33 2016 +0100
  51. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  52. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000