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git01.mediatek.com / filogic / atf / 1ab5c60e63e794523834a700034cdf5197e66495 / plat / arm / css / sgi / sgi_plat_v2.c
  1. 1676ace feat(plat/arm): add memory map entry for CPER memory region by Omkar Anand Kulkarni · 2 years, 1 month ago
  2. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  3. 9c07f60 feat(sgi): add page table translation entry for secure uart by Rohit Mathew · 2 years, 11 months ago
  4. 0123196 Revert "feat(sgi): add page table translation entry for secure uart" by Madhukar Pappireddy · 2 years, 8 months ago
  5. 62a3b91 feat(sgi): add page table translation entry for secure uart by Rohit Mathew · 2 years, 11 months ago
  6. ccae8a1 feat(rdn2): add board support for rdn2cfg2 variant by Aditya Angadi · 3 years, 3 months ago
  7. 2994dc0 plat/sgi: allow usage of secure partions on rdn2 platform by Omkar Anand Kulkarni · 3 years, 10 months ago
  8. aaa7b27 plat/arm/sgi: adapt to changes in memory map by Aditya Angadi · 4 years ago