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git01.mediatek.com / filogic / atf / 1778b41e6670f37086c242ba00a55289e136d8d7 / plat / nvidia / tegra / soc
  1. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  2. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · 9 years ago
  3. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · 9 years ago
  4. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · 9 years ago
  5. e82e29c Implement plat_get_syscnt_freq2 on platforms by Antonio Nino Diaz · 8 years ago
  6. 3c0087a Move `plat_get_syscnt_freq()` to arm_common.c by Yatharth Kochar · 9 years ago
  7. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · 9 years ago
  8. 8b82fae Tegra: introduce per-soc system reset handler by Varun Wadekar · 9 years ago
  9. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  10. e98a146 Tegra132: set TZDRAM_BASE to 0xF5C00000 by Varun Wadekar · 9 years ago
  11. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · 9 years ago
  12. 0f3baa0 Tegra: Support for Tegra's T132 platforms by Varun Wadekar · 9 years ago
  13. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · 9 years ago
  14. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  15. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  16. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · 9 years ago
  17. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · 9 years ago
  18. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · 9 years ago
  19. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago