Log - 14eaede642420b0be417a91d77c9161fca2f046a - filogic/atf

69ce101 Tegra: enable ECC/Parity protection for Cortex-A57 CPUs by Varun Wadekar · Thu May 12 13:43:33 2016 -0700
25e658e Tegra: include platform_def.h to access UART macros by Varun Wadekar · Tue Apr 26 11:38:38 2016 -0700
1ec441e Tegra: relocate code to BL31_BASE during cold boot by Varun Wadekar · Thu Mar 24 15:34:24 2016 -0700
d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · Thu Oct 29 10:37:28 2015 +0530
39f87d1 Tegra: use ClusterId for calculating core position by Varun Wadekar · Tue Sep 22 13:45:07 2015 +0530
b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · Tue Sep 22 13:33:56 2015 +0530
e7ae6db Disable PL011 UART before configuring it by Juan Castillo · Thu Nov 26 14:52:15 2015 +0000
a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · Fri Aug 07 10:03:00 2015 +0530
4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · Fri Aug 21 15:56:02 2015 +0530
d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · Thu Jul 16 09:46:28 2015 +0530
b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530