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git01.mediatek.com / filogic / atf / 14b5c060f30afb0bd9d000a9838c46d2c30262c6 / docs / plat / xilinx-versal.rst
  1. 82252a4 feat(plat/versal): add support for SLS mitigation by Venkatesh Yadav Abbarapu · Tue Jul 20 22:27:32 2021 -0600
  2. 17a12ce plat:xilinx:versal: Add JTAG DCC support by Venkatesh Yadav Abbarapu · Fri Nov 27 08:42:14 2020 -0700
  3. 9156ffd xilinx: versal: PLM to ATF handover by Venkatesh Yadav Abbarapu · Wed Jan 22 21:23:20 2020 -0700
  4. cbc9005 plat: xilinx: versal: Make silicon default build target by Siva Durga Prasad Paladugu · Wed Jul 10 16:15:19 2019 +0530
  5. f3653a6 doc: Reformat platform port documents by Paul Beesley · Wed May 22 11:22:44 2019 +0100[Renamed (90%) from docs/plat/xilinx-versal.md]
  6. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · Tue Sep 25 18:44:58 2018 +0530