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git01.mediatek.com / filogic / atf / 10bb1a83e646d4f00d6d60c3cff965ad3c46b9d9 / include / arch / aarch32
  1. 1f55c41 refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED by Andre Przywara · 1 year, 10 months ago
  2. 906776e refactor(amu): use new AMU feature check routines by Andre Przywara · 1 year, 9 months ago
  3. 44e33e0 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · 2 years ago
  4. f3e8cfc refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED by Andre Przywara · 2 years ago
  5. 4f8eada Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration by Manish Pandey · 1 year, 8 months ago
  6. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  7. 183638f style: remove useless trailing semicolon and line continuations by Elyes Haouas · 1 year, 9 months ago
  8. 06ea44e refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED by Andre Przywara · 2 years ago
  9. bb0db3b refactor(cpufeat): wrap CPU ID register field isolation by Andre Przywara · 1 year, 10 months ago
  10. 69508e9 feat(debug): add AARCH32 CP15 fault registers by Yann Gautier · 5 years ago
  11. d4e2503 feat(gic): add APIs to raise NS and S-EL1 SGIs by Florian Lugou · 3 years, 2 months ago
  12. 0824b45 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · 2 years, 9 months ago
  13. 74b7e44 feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX by johpow01 · 3 years ago
  14. a40141d refactor(amu): detect architected counters at runtime by Chris Kay · 3 years, 6 months ago
  15. a5fde28 refactor(amu): factor out register accesses by Chris Kay · 3 years, 6 months ago
  16. b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 3 years, 1 month ago
  17. 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · 3 years, 4 months ago
  18. 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 3 years, 4 months ago
  19. f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · 3 years, 5 months ago
  20. f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 3 years, 4 months ago
  21. 514e59c Add PIE support for AARCH32 by Yann Gautier · 4 years, 1 month ago
  22. e57bce8 Avoid the use of linker *_SIZE__ macros by Yann Gautier · 4 years, 3 months ago
  23. 08fec33 arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms by Chris Kay · 3 years, 8 months ago
  24. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · 4 years, 1 month ago
  25. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years ago
  26. 5c29cba aarch64/arm: Add compiler barrier to barrier instructions by Andre Przywara · 4 years, 1 month ago
  27. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · 4 years, 3 months ago
  28. 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · 4 years, 4 months ago
  29. 90d6532 Provide a hint to power controller for DSU cluster power down by Madhukar Pappireddy · 5 years ago
  30. 019b4f8 locks: bakery: use is_dcache_enabled() helper by Masahiro Yamada · 4 years, 8 months ago
  31. a5c6636 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · 4 years, 8 months ago
  32. 84d681f Merge "el3_entrypoint_common: avoid overwriting arg3" into integration by Manish Pandey · 4 years, 8 months ago
  33. bfe7bb6 Use Speculation Barrier instruction for v8.5 cores by Madhukar Pappireddy · 4 years, 8 months ago
  34. fcbcd6f aarch32: stop speculative execution past exception returns by Madhukar Pappireddy · 4 years, 9 months ago
  35. c241b57 el3_entrypoint_common: avoid overwriting arg3 by Yann Gautier · 4 years, 10 months ago
  36. 20be077 Changes to support updated register usage in SMCCC v1.2 by Madhukar Pappireddy · 5 years ago
  37. d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 5 years ago
  38. 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 5 years ago
  39. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · 5 years ago
  40. 5553417 SSBS: init SPSR register with default SSBS value by John Tsichritzis · 5 years ago
  41. 35e08da console: update skeleton by Ambroise Vincent · 5 years ago
  42. 007d745 arch: add some defines for generic timer registers by Yann Gautier · 6 years ago
  43. 457c64e aarch32: Allow compiling with soft-float toolchain by Manish Pandey · 6 years ago
  44. 0a0ca8b Console: remove deprecated finish_console_register by Ambroise Vincent · 6 years ago
  45. f5fdfbc Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · 6 years ago
  46. 404184d Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd by Antonio Niño Díaz · 6 years ago
  47. 078e66f plat/arm: Support for Cortex A5 in FVP Versatile Express platform by Usama Arif · 6 years ago
  48. b69ac08 Division functionality for cores that dont have divide hardware. by Usama Arif · 6 years ago
  49. 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
  50. d29d21e drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · 6 years ago
  51. c326c34 xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · 6 years ago
  52. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  53. 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 6 years ago