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git01.mediatek.com / filogic / atf / 0e1c7f01288b5cad3f5891f8907804b8ae70d1d4 / include / arch / aarch32 / arch.h
  1. 6e2fd8b fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly by Boyan Karatotev · 1 year, 9 months ago
  2. 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · 1 year, 9 months ago
  3. 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · 1 year, 9 months ago
  4. 54d5791 feat(cpufeat): add AArch32 PAN detection support by Andre Przywara · 1 year, 6 months ago
  5. 9b468c3 Merge changes I1bfa797e,I0ec7a70e into integration by Manish Pandey · 1 year, 6 months ago
  6. 2be03c0 fix(tree): correct some typos by Elyes Haouas · 1 year, 9 months ago
  7. 7fe0352 feat(errata_abi): errata management firmware interface by Sona Mathew · 2 years ago
  8. 69508e9 feat(debug): add AARCH32 CP15 fault registers by Yann Gautier · 6 years ago
  9. 74b7e44 feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX by johpow01 · 3 years ago
  10. a40141d refactor(amu): detect architected counters at runtime by Chris Kay · 3 years, 6 months ago
  11. a5fde28 refactor(amu): factor out register accesses by Chris Kay · 3 years, 6 months ago
  12. 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 3 years, 4 months ago
  13. f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 3 years, 5 months ago
  14. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · 4 years, 2 months ago
  15. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years ago
  16. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · 4 years, 4 months ago
  17. 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · 4 years, 4 months ago
  18. 90d6532 Provide a hint to power controller for DSU cluster power down by Madhukar Pappireddy · 5 years ago
  19. a5c6636 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · 4 years, 8 months ago
  20. 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 5 years ago
  21. 5553417 SSBS: init SPSR register with default SSBS value by John Tsichritzis · 5 years ago
  22. 007d745 arch: add some defines for generic timer registers by Yann Gautier · 6 years ago
  23. f5fdfbc Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · 6 years ago
  24. 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
  25. d29d21e drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · 6 years ago
  26. c326c34 xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · 6 years ago
  27. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  28. 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 6 years ago[Renamed from include/lib/aarch32/arch.h]
  29. 0f3a004 Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 6 years ago