Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 08554a65bf6d160900f235244facc1967b6ec029 / plat / nvidia / tegra / soc / t210
  1. 08554a6 Tegra210: memmap all the IRAM memory banks by Varun Wadekar · 7 years ago
  2. 7baa94a Tegra210: increase MAX_XLAT_TABLES and MAX_MMAP_REGIONS by Varun Wadekar · 7 years ago
  3. 809c773 Tegra210B01: initialize DRBG on boot and resume by Sam Payne · 7 years ago
  4. a6a357f Tegra210: bpmp: power management interface by Varun Wadekar · 7 years ago
  5. 21eea97 Tegra210B01: SE1 and SE2/PKA1 context save (atomic) by Marvin Hsu · 7 years ago
  6. e34bc3d Tegra: retrieve power domain tree from the platforms by Varun Wadekar · 7 years ago
  7. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  8. 9f4a7d3 Tegra: support for native GICv2 drivers by Varun Wadekar · 6 years ago
  9. 92cea4a tegra: Fix mmap_region_t struct mismatch by Andreas Färber · 6 years ago
  10. e363146 Fix order of remaining platform #includes by Isla Mitchell · 7 years ago
  11. 66231d1 Tegra: enable 'signed-comparison' compilation warning/errors by Varun Wadekar · 7 years ago
  12. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  13. b91b5fc Tegra210: implement 'get_target_pwr_state' handler by Varun Wadekar · 7 years ago
  14. 4d160ac Tegra: memmap Tegra micro-seconds timer controller by Steven Kao · 8 years ago
  15. 1108fc6 plat/tegra: Enable Cortex-A53 erratum 855873 workaround by Andre Przywara · 8 years ago
  16. ed3c62b Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs by Varun Wadekar · 7 years ago
  17. 20e9fef Tegra210: assert if afflvl0/1 have incorrect state-ids by Harvey Hsieh · 8 years ago
  18. 1edb882 Tegra210: new TZDRAM base address by Varun Wadekar · 8 years ago
  19. dba8007 Tegra210: set core power state during cluster power down by Varun Wadekar · 8 years ago
  20. b7b4575 Tegra: GIC: enable FIQ interrupt handling by Varun Wadekar · 9 years ago
  21. 6eec6d6 Tegra: allow individual SoCs to restore their settings by Varun Wadekar · 8 years ago
  22. 6077dce Tegra: enable PSCI extended state ID processing by Varun Wadekar · 8 years ago
  23. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · 9 years ago
  24. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · 9 years ago
  25. 7a9a285 Tegra: Memory Controller Driver (v1) by Varun Wadekar · 9 years ago
  26. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  27. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · 9 years ago
  28. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · 9 years ago
  29. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · 9 years ago
  30. e82e29c Implement plat_get_syscnt_freq2 on platforms by Antonio Nino Diaz · 8 years ago
  31. 3c0087a Move `plat_get_syscnt_freq()` to arm_common.c by Yatharth Kochar · 8 years ago
  32. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · 9 years ago
  33. 8b82fae Tegra: introduce per-soc system reset handler by Varun Wadekar · 9 years ago
  34. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  35. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · 9 years ago
  36. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · 9 years ago
  37. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  38. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  39. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · 9 years ago
  40. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · 9 years ago
  41. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · 9 years ago
  42. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago