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git01.mediatek.com / filogic / atf / 04c74b98c801cf2c2585de27307f65f17b9e951a / plat / rockchip / rk3399 / drivers / dram / dfs.c
  1. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · 8 years ago
  2. 52512c2 rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0 by Lin Huang · 8 years ago
  3. dc8e82e rockchip: rk3399: enable CA training when do ddr dfs by Lin Huang · 8 years ago
  4. 0e8909d rockchip: rk3399: Enable per CS training at 666MHz by Derek Basehore · 8 years ago
  5. e13bc54 rockchip: rk3399: add support for ddrfreq suspend/resume by Derek Basehore · 7 years ago
  6. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · 8 years ago
  7. b106512 rk3399: dram: making phy into dll bypass mode at low frequency by Derek Basehore · 8 years ago
  8. ff461d0 rockchip: rk3399: dram: remove dram_init and dts_timing_receive function by Derek Basehore · 8 years ago
  9. 8bc1667 rockchip: Change dmc register accesses to ATF style for rk3399 by Caesar Wang · 8 years ago
  10. a845690 rockchip: Break out common dram code for rk3399 by Caesar Wang · 8 years ago