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git01.mediatek.com / filogic / atf / 0242df04644f151d400bc375ea5a84db081caab3 / plat / xilinx / zynqmp / zynqmp_def.h
  1. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · Wed Nov 16 15:50:14 2016 -0800
  2. 836418d zynqmp: Fix UART1 base address by Soren Brinkmann · Fri May 27 08:56:53 2016 -0700
  3. cfcb1a2 zynqmp: Do not alter system counter by Soren Brinkmann · Fri Sep 16 10:31:06 2016 -0700
  4. cf4e714 zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1 by Naga Sureshkumar Relli · Fri Jul 01 12:46:43 2016 +0530
  5. 99c0d7b zynqmp: Add option to select between Cadence UARTs by Soren Brinkmann · Fri Jun 10 09:57:14 2016 -0700
  6. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · Fri Apr 22 10:02:46 2016 -0700
  7. ef8f559 zynqmp: FSBL->ATF handover by Michal Simek · Mon Jun 15 14:22:50 2015 +0200
  8. b43d943 zynqmp: Introduce zynqmp_get_bootmode by Soren Brinkmann · Mon Apr 18 11:49:42 2016 -0700
  9. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · Thu Apr 14 10:27:00 2016 -0700
  10. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800