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git01.mediatek.com / filogic / atf / 00960ba1f8a1d3882b20ef00d63b3bfb38d2f39d / plat / rockchip / rk3399 / drivers / m0
  1. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · 6 years ago
  2. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  3. 397046c rockchip: rk3399: Move DQS drive strength setting to M0 by Derek Basehore · 7 years ago
  4. 84afaaf rockchip: Add MIN() and MAX() macros back to M0 code by Julius Werner · 7 years ago
  5. f585246 rockchip: Clean up M0 Makefile, clarify float-abi by Julius Werner · 7 years ago
  6. b4bcc1d rockchip: Clean up header and referenced files by Xing Zheng · 7 years ago
  7. fc0552d rockchip: rk3399: Don't wait for vblank in M0 for ddrfreq by Derek Basehore · 7 years ago
  8. 2510366 rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs by Lin Huang · 8 years ago
  9. 3b0eb7e rockchip: rk3399: check vop status when we wait dma finish flag by Lin Huang · 8 years ago
  10. e7c2422 rockchip: rk3399: add stopwatch functions to m0 by Lin Huang · 8 years ago
  11. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · 8 years ago
  12. aae6be4 rockchip: update the raw read/write APIs for M0 by Xing Zheng · 8 years ago
  13. 5c979f1 rockchip: Build m0 firmware without standard libraries by Patrick Georgi · 8 years ago
  14. 844782d rockchip: Add proper dependency tracking to M0 Makefile by Julius Werner · 8 years ago
  15. 705aeeb rockchip: Clean up parent directory creation for M0 by Julius Werner · 8 years ago
  16. b400374 rockchip: add M0 source code and build system for RK3399 by Caesar Wang · 8 years ago