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Antonio Nino Diaz7289f922017-11-09 11:34:09 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef ARM_SPM_DEF_H
7#define ARM_SPM_DEF_H
Antonio Nino Diaz7289f922017-11-09 11:34:09 +00008
9#include <arm_def.h>
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000010#include <utils_def.h>
11#include <xlat_tables_defs.h>
12
13/*
14 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
15 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
16 * at the base of DRAM.
17 */
18#define ARM_SP_IMAGE_BASE BL32_BASE
19#define ARM_SP_IMAGE_LIMIT BL32_LIMIT
20/* The maximum size of the S-EL0 payload can be 3MB */
21#define ARM_SP_IMAGE_SIZE ULL(0x300000)
22
23#ifdef IMAGE_BL2
24/* SPM Payload memory. Mapped as RW in BL2. */
25#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \
26 ARM_SP_IMAGE_BASE, \
27 ARM_SP_IMAGE_SIZE, \
28 MT_MEMORY | MT_RW | MT_SECURE)
29#endif
30#ifdef IMAGE_BL31
31/* SPM Payload memory. Mapped as code in S-EL1 */
32#define ARM_SP_IMAGE_MMAP MAP_REGION2( \
33 ARM_SP_IMAGE_BASE, \
34 ARM_SP_IMAGE_BASE, \
35 ARM_SP_IMAGE_SIZE, \
36 MT_CODE | MT_SECURE | MT_USER, \
37 PAGE_SIZE)
38#endif
39
40/*
41 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into
42 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission
43 * from S-EL0. Placed after SPM Payload memory.
44 */
45#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE)
46#define PLAT_SPM_BUF_SIZE ULL(0x100000)
47
48#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \
49 PLAT_SPM_BUF_BASE, \
50 PLAT_SPM_BUF_SIZE, \
51 MT_RW_DATA | MT_SECURE)
52#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \
53 PLAT_SPM_BUF_BASE, \
54 PLAT_SPM_BUF_BASE, \
55 PLAT_SPM_BUF_SIZE, \
56 MT_RO_DATA | MT_SECURE | MT_USER,\
57 PAGE_SIZE)
58
59/*
60 * Memory shared between Normal world and S-EL0 for passing data during service
61 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
62 * S-EL0.
63 */
64#define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
65#define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
66#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
67 ARM_SP_IMAGE_NS_BUF_BASE, \
68 ARM_SP_IMAGE_NS_BUF_BASE, \
69 ARM_SP_IMAGE_NS_BUF_SIZE, \
70 MT_RW_DATA | MT_NS | MT_USER, \
71 PAGE_SIZE)
72
73/*
74 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory
Sughosh Ganu5f212942018-05-16 15:35:25 +053075 * shared between Secure and Non-secure worlds, or after the platform specific
76 * buffers, if defined. First there is the stack memory for all CPUs and then
77 * there is the common heap memory. Both are mapped with RW permissions.
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000078 */
Sughosh Ganu5f212942018-05-16 15:35:25 +053079#define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000080#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
81#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
82 PLAT_SP_IMAGE_STACK_PCPU_SIZE)
83
84#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \
85 ARM_SP_IMAGE_STACK_TOTAL_SIZE)
86#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE)
87
88#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \
89 PLAT_SP_IMAGE_STACK_BASE, \
90 PLAT_SP_IMAGE_STACK_BASE, \
91 (ARM_SP_IMAGE_LIMIT - \
92 PLAT_SP_IMAGE_STACK_BASE), \
93 MT_RW_DATA | MT_SECURE | MT_USER,\
94 PAGE_SIZE)
95
96/* Total number of memory regions with distinct properties */
97#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
98
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000099/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
100#define PLAT_SPM_COOKIE_0 ULL(0)
101#define PLAT_SPM_COOKIE_1 ULL(0)
102
Antonio Nino Diazb86edcb2018-10-30 11:12:42 +0000103/*
104 * Max number of elements supported by SPM in this platform. The defines below
105 * are used to allocate memory at compile time for different arrays in SPM.
106 */
107#define PLAT_SPM_MEM_REGIONS_MAX U(80)
108#define PLAT_SPM_NOTIFICATIONS_MAX U(30)
109#define PLAT_SPM_SERVICES_MAX U(30)
110
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000111#endif /* ARM_SPM_DEF_H */