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Anson Huang62f8f7a2018-06-11 12:54:05 +08001/*
Deepika Bhavnani92efb232019-12-13 10:47:06 -06002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Anson Huang62f8f7a2018-06-11 12:54:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010011
Anson Huang62f8f7a2018-06-11 12:54:05 +080012#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
13#define PLATFORM_LINKER_ARCH aarch64
14
15#define PLATFORM_STACK_SIZE 0X400
16#define CACHE_WRITEBACK_GRANULE 64
17
Deepika Bhavnani92efb232019-12-13 10:47:06 -060018#define PLAT_PRIMARY_CPU U(0x0)
19#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
20#define PLATFORM_CLUSTER_COUNT U(2)
21#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
22#define PLATFORM_CLUSTER1_CORE_COUNT U(2)
Anson Huang62f8f7a2018-06-11 12:54:05 +080023#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
24 PLATFORM_CLUSTER1_CORE_COUNT)
25
26#define IMX_PWR_LVL0 MPIDR_AFFLVL0
27#define IMX_PWR_LVL1 MPIDR_AFFLVL1
28#define IMX_PWR_LVL2 MPIDR_AFFLVL2
29
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010030#define PWR_DOMAIN_AT_MAX_LVL U(1)
31#define PLAT_MAX_PWR_LVL U(2)
32#define PLAT_MAX_OFF_STATE U(2)
33#define PLAT_MAX_RET_STATE U(1)
Anson Huang62f8f7a2018-06-11 12:54:05 +080034
35#define BL31_BASE 0x80000000
36#define BL31_LIMIT 0x80020000
37
38#define PLAT_GICD_BASE 0x51a00000
Anson Huang62f8f7a2018-06-11 12:54:05 +080039#define PLAT_GICR_BASE 0x51b00000
Anson Huang62f8f7a2018-06-11 12:54:05 +080040#define PLAT_CCI_BASE 0x52090000
Anson Huang62f8f7a2018-06-11 12:54:05 +080041#define CLUSTER0_CCI_SLVAE_IFACE 3
42#define CLUSTER1_CCI_SLVAE_IFACE 4
43#define IMX_BOOT_UART_BASE 0x5a060000
Anson Huang62f8f7a2018-06-11 12:54:05 +080044#define IMX_BOOT_UART_BAUDRATE 115200
45#define IMX_BOOT_UART_CLK_IN_HZ 24000000
46#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
47#define PLAT__CRASH_UART_CLK_IN_HZ 24000000
48#define IMX_CONSOLE_BAUDRATE 115200
49#define SC_IPC_BASE 0x5d1b0000
Anson Huangad192dc2019-01-24 16:09:52 +080050#define IMX_GPT_LPCG_BASE 0x5d540000
51#define IMX_GPT_BASE 0x5d140000
52#define IMX_WUP_IRQSTR_BASE 0x51090000
53#define IMX_REG_BASE 0x50000000
54#define IMX_REG_SIZE 0x10000000
Anson Huang62f8f7a2018-06-11 12:54:05 +080055
56#define COUNTER_FREQUENCY 8000000 /* 8MHz */
57
58/* non-secure uboot base */
59#define PLAT_NS_IMAGE_OFFSET 0x80020000
60
61#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
62#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
63
64#define MAX_XLAT_TABLES 8
65#define MAX_MMAP_REGIONS 12
66
67#define DEBUG_CONSOLE 0
68#define DEBUG_CONSOLE_A53 0
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010069
70#endif /* PLATFORM_DEF_H */