blob: 13e1353258c8c79c2697bb78c583a492ff82ec04 [file] [log] [blame]
Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Samuel Hollandb8566642017-08-12 04:07:39 -05007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Samuel Hollandb8566642017-08-12 04:07:39 -05009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <drivers/arm/gicv2.h>
14#include <drivers/delay_timer.h>
15#include <lib/mmio.h>
16#include <lib/psci/psci.h>
17#include <plat/common/platform.h>
18
Samuel Holland0a9018c2017-08-12 04:07:39 -050019#include <sunxi_cpucfg.h>
Andre Przywara456208a2018-10-14 12:02:02 +010020#include <sunxi_mmap.h>
21#include <sunxi_private.h>
Samuel Hollandb8566642017-08-12 04:07:39 -050022
Clément Péron3071a1f2019-04-09 00:15:06 +020023#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
24#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
25#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
Samuel Hollandb8566642017-08-12 04:07:39 -050026
Samuel Holland0a9018c2017-08-12 04:07:39 -050027#define mpidr_is_valid(mpidr) ( \
28 MPIDR_AFFLVL3_VAL(mpidr) == 0 && \
29 MPIDR_AFFLVL2_VAL(mpidr) == 0 && \
30 MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \
31 MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER)
32
33static int sunxi_pwr_domain_on(u_register_t mpidr)
34{
35 if (mpidr_is_valid(mpidr) == 0)
36 return PSCI_E_INTERN_FAIL;
37
Samuel Hollandc629daf2019-02-17 15:33:33 -060038 sunxi_cpu_on(mpidr);
Samuel Holland0a9018c2017-08-12 04:07:39 -050039
40 return PSCI_E_SUCCESS;
41}
42
43static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
44{
45 gicv2_cpuif_disable();
46}
47
Andre Przywara6d0b81b2018-09-28 00:43:32 +010048static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
49{
Samuel Hollandc629daf2019-02-17 15:33:33 -060050 sunxi_cpu_off(read_mpidr());
Andre Przywara6d0b81b2018-09-28 00:43:32 +010051
52 while (1)
53 wfi();
54}
55
Samuel Holland0a9018c2017-08-12 04:07:39 -050056static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
57{
58 gicv2_pcpu_distif_init();
59 gicv2_cpuif_enable();
60}
61
Samuel Hollandb8566642017-08-12 04:07:39 -050062static void __dead2 sunxi_system_off(void)
63{
Samuel Holland321c0ab2017-08-12 04:07:39 -050064 /* Turn off all secondary CPUs */
Samuel Hollandc629daf2019-02-17 15:33:33 -060065 sunxi_disable_secondary_cpus(read_mpidr());
Samuel Holland321c0ab2017-08-12 04:07:39 -050066
Icenowy Zhengbd57eb52018-07-22 21:52:50 +080067 sunxi_power_down();
Samuel Hollandb8566642017-08-12 04:07:39 -050068}
69
70static void __dead2 sunxi_system_reset(void)
71{
72 /* Reset the whole system when the watchdog times out */
73 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
74 /* Enable the watchdog with the shortest timeout (0.5 seconds) */
75 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
76 /* Wait for twice the watchdog timeout before panicking */
77 mdelay(1000);
78
79 ERROR("PSCI: System reset failed\n");
80 wfi();
81 panic();
82}
83
Samuel Holland0a9018c2017-08-12 04:07:39 -050084static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
85{
86 /* The non-secure entry point must be in DRAM */
Andre Przywara9f3cb8c2018-06-22 00:48:15 +010087 if (ns_entrypoint >= SUNXI_DRAM_BASE)
Samuel Holland0a9018c2017-08-12 04:07:39 -050088 return PSCI_E_SUCCESS;
89
90 return PSCI_E_INVALID_ADDRESS;
91}
92
Samuel Hollandb8566642017-08-12 04:07:39 -050093static plat_psci_ops_t sunxi_psci_ops = {
Samuel Holland0a9018c2017-08-12 04:07:39 -050094 .pwr_domain_on = sunxi_pwr_domain_on,
95 .pwr_domain_off = sunxi_pwr_domain_off,
Andre Przywara6d0b81b2018-09-28 00:43:32 +010096 .pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi,
Samuel Holland0a9018c2017-08-12 04:07:39 -050097 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
Samuel Hollandb8566642017-08-12 04:07:39 -050098 .system_off = sunxi_system_off,
99 .system_reset = sunxi_system_reset,
Samuel Holland0a9018c2017-08-12 04:07:39 -0500100 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
Samuel Hollandb8566642017-08-12 04:07:39 -0500101};
102
103int plat_setup_psci_ops(uintptr_t sec_entrypoint,
104 const plat_psci_ops_t **psci_ops)
105{
106 assert(psci_ops);
107
Samuel Holland0a9018c2017-08-12 04:07:39 -0500108 for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
109 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
110 sec_entrypoint & 0xffffffff);
111 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
112 sec_entrypoint >> 32);
113 }
114
Samuel Hollandb8566642017-08-12 04:07:39 -0500115 *psci_ops = &sunxi_psci_ops;
116
117 return 0;
118}