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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Douglas Raillard21362a92016-12-02 13:51:54 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl2_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010038 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010039}
40
41
42SECTIONS
43{
44 . = BL2_BASE;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045 ASSERT(. == ALIGN(4096),
46 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010048#if SEPARATE_CODE_AND_RODATA
49 .text . : {
50 __TEXT_START__ = .;
51 *bl2_entrypoint.o(.text*)
52 *(.text*)
53 *(.vectors)
54 . = NEXT(4096);
55 __TEXT_END__ = .;
56 } >RAM
57
58 .rodata . : {
59 __RODATA_START__ = .;
60 *(.rodata*)
61
62 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
63 . = ALIGN(8);
64 __PARSER_LIB_DESCS_START__ = .;
65 KEEP(*(.img_parser_lib_descs))
66 __PARSER_LIB_DESCS_END__ = .;
67
68 . = NEXT(4096);
69 __RODATA_END__ = .;
70 } >RAM
71#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000072 ro . : {
73 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000074 *bl2_entrypoint.o(.text*)
75 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000076 *(.rodata*)
Juan Castillo8e55d932015-04-02 09:48:16 +010077
78 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
79 . = ALIGN(8);
80 __PARSER_LIB_DESCS_START__ = .;
81 KEEP(*(.img_parser_lib_descs))
82 __PARSER_LIB_DESCS_END__ = .;
83
Achin Guptab739f222014-01-18 16:50:09 +000084 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000085 __RO_END_UNALIGNED__ = .;
86 /*
87 * Memory page(s) mapped to this section will be marked as
88 * read-only, executable. No RW data from the next section must
89 * creep in. Ensure the rest of the current memory page is unused.
90 */
91 . = NEXT(4096);
92 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010094#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010095
Achin Guptae9c4a642015-09-11 16:03:13 +010096 /*
97 * Define a linker symbol to mark start of the RW memory area for this
98 * image.
99 */
100 __RW_START__ = . ;
101
Douglas Raillard306593d2017-02-24 18:14:15 +0000102 /*
103 * .data must be placed at a lower address than the stacks if the stack
104 * protector is enabled. Alternatively, the .data.stack_protector_canary
105 * section can be placed independently of the main .data section.
106 */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000107 .data . : {
108 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000109 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000110 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 } >RAM
112
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000113 stacks (NOLOAD) : {
114 __STACKS_START__ = .;
115 *(tzfw_normal_stacks)
116 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117 } >RAM
118
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000119 /*
120 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000121 * Its base address should be 16-byte aligned for better performance of the
122 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000123 */
124 .bss : ALIGN(16) {
125 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000126 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000128 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129 } >RAM
130
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000131 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000132 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000133 * Removing them from .bss avoids forcing 4K alignment on
134 * the .bss section and eliminates the unecessary zero init
135 */
136 xlat_table (NOLOAD) : {
137 *(xlat_table)
138 } >RAM
139
Soby Mathew2ae20432015-01-08 18:02:44 +0000140#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000141 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000142 * The base address of the coherent memory section must be page-aligned (4K)
143 * to guarantee that the coherent data are stored on their own pages and
144 * are not mixed with normal data. This is required to set up the correct
145 * memory attributes for the coherent data page tables.
146 */
147 coherent_ram (NOLOAD) : ALIGN(4096) {
148 __COHERENT_RAM_START__ = .;
149 *(tzfw_coherent_mem)
150 __COHERENT_RAM_END_UNALIGNED__ = .;
151 /*
152 * Memory page(s) mapped to this section will be marked
153 * as device memory. No other unexpected data must creep in.
154 * Ensure the rest of the current memory page is unused.
155 */
156 . = NEXT(4096);
157 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000159#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160
Achin Guptae9c4a642015-09-11 16:03:13 +0100161 /*
162 * Define a linker symbol to mark end of the RW memory area for this
163 * image.
164 */
165 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000166 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000168 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000169
170#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000171 __COHERENT_RAM_UNALIGNED_SIZE__ =
172 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000173#endif
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100174
175 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176}