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Soby Mathew748be1d2016-05-05 14:10:46 +01001/*
Olivier Deprez7d0299f2021-05-25 12:06:03 +02002 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
Soby Mathew748be1d2016-05-05 14:10:46 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew748be1d2016-05-05 14:10:46 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <stdbool.h>
9#include <string.h>
10
11#include <platform_def.h>
12
Soby Mathew748be1d2016-05-05 14:10:46 +010013#include <arch.h>
14#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <common/bl_common.h>
Soby Mathew748be1d2016-05-05 14:10:46 +010016#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/el3_runtime/context_mgmt.h>
18#include <lib/extensions/amu.h>
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010019#include <lib/extensions/sys_reg_trace.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +010020#include <lib/extensions/trf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <lib/utils.h>
Soby Mathew748be1d2016-05-05 14:10:46 +010022
23/*******************************************************************************
24 * Context management library initialisation routine. This library is used by
25 * runtime services to share pointers to 'cpu_context' structures for the secure
26 * and non-secure states. Management of the structures and their associated
27 * memory is not done by the context management library e.g. the PSCI service
28 * manages the cpu context used for entry from and exit to the non-secure state.
29 * The Secure payload manages the context(s) corresponding to the secure state.
30 * It also uses this library to get access to the non-secure
31 * state cpu context pointers.
32 ******************************************************************************/
33void cm_init(void)
34{
35 /*
36 * The context management library has only global data to initialize, but
37 * that will be done when the BSS is zeroed out
38 */
39}
40
41/*******************************************************************************
42 * The following function initializes the cpu_context 'ctx' for
43 * first use, and sets the initial entrypoint state as specified by the
44 * entry_point_info structure.
45 *
46 * The security state to initialize is determined by the SECURE attribute
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010047 * of the entry_point_info.
Soby Mathew748be1d2016-05-05 14:10:46 +010048 *
49 * The EE and ST attributes are used to configure the endianness and secure
50 * timer availability for the new execution context.
51 *
52 * To prepare the register state for entry call cm_prepare_el3_exit() and
53 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
Olivier Deprez7d0299f2021-05-25 12:06:03 +020054 * cm_el1_sysregs_context_restore().
Soby Mathew748be1d2016-05-05 14:10:46 +010055 ******************************************************************************/
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010056void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
Soby Mathew748be1d2016-05-05 14:10:46 +010057{
58 unsigned int security_state;
59 uint32_t scr, sctlr;
60 regs_t *reg_ctx;
61
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000062 assert(ctx != NULL);
Soby Mathew748be1d2016-05-05 14:10:46 +010063
64 security_state = GET_SECURITY_STATE(ep->h.attr);
65
66 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000067 zeromem(ctx, sizeof(*ctx));
Soby Mathew748be1d2016-05-05 14:10:46 +010068
Soby Mathewb4a970a2016-08-31 12:34:33 +010069 reg_ctx = get_regs_ctx(ctx);
70
Soby Mathew748be1d2016-05-05 14:10:46 +010071 /*
72 * Base the context SCR on the current value, adjust for entry point
73 * specific requirements
74 */
75 scr = read_scr();
76 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT);
77
78 if (security_state != SECURE)
79 scr |= SCR_NS_BIT;
80
Soby Mathew748be1d2016-05-05 14:10:46 +010081 if (security_state != SECURE) {
Soby Mathewa993c422016-09-29 14:15:57 +010082 /*
David Cunadofee86532017-04-13 22:38:29 +010083 * Set up SCTLR for the Non-secure context.
84 *
85 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
86 *
87 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
88 * required by PSCI specification)
89 *
90 * Set remaining SCTLR fields to their architecturally defined
91 * values. Some fields reset to an IMPLEMENTATION DEFINED value:
92 *
93 * SCTLR.TE: Set to zero so that exceptions to an Exception
94 * Level executing at PL1 are taken to A32 state.
95 *
96 * SCTLR.V: Set to zero to select the normal exception vectors
97 * with base address held in VBAR.
Soby Mathewa993c422016-09-29 14:15:57 +010098 */
David Cunadofee86532017-04-13 22:38:29 +010099 assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) ==
100 (EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT));
101
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000102 sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
David Cunadofee86532017-04-13 22:38:29 +0100103 sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT));
Soby Mathew748be1d2016-05-05 14:10:46 +0100104 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
105 }
106
David Cunadofee86532017-04-13 22:38:29 +0100107 /*
108 * The target exception level is based on the spsr mode requested. If
109 * execution is requested to hyp mode, HVC is enabled via SCR.HCE.
110 */
Soby Mathew748be1d2016-05-05 14:10:46 +0100111 if (GET_M32(ep->spsr) == MODE32_hyp)
112 scr |= SCR_HCE_BIT;
113
David Cunadofee86532017-04-13 22:38:29 +0100114 /*
115 * Store the initialised values for SCTLR and SCR in the cpu_context.
116 * The Hyp mode registers are not part of the saved context and are
117 * set-up in cm_prepare_el3_exit().
118 */
Soby Mathew748be1d2016-05-05 14:10:46 +0100119 write_ctx_reg(reg_ctx, CTX_SCR, scr);
120 write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
121 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
122
123 /*
124 * Store the r0-r3 value from the entrypoint into the context
125 * Use memcpy as we are in control of the layout of the structures
126 */
127 memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t));
128}
129
130/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000131 * Enable architecture extensions on first entry to Non-secure world.
132 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
133 * it is zero.
134 ******************************************************************************/
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100135static void enable_extensions_nonsecure(bool el2_unused)
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000136{
137#if IMAGE_BL32
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100138#if ENABLE_AMU
139 amu_enable(el2_unused);
140#endif
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100141
142#if ENABLE_SYS_REG_TRACE_FOR_NS
143 sys_reg_trace_enable();
144#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100145
146#if ENABLE_TRF_FOR_NS
147 trf_enable();
148#endif /* ENABLE_TRF_FOR_NS */
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000149#endif
150}
151
152/*******************************************************************************
Soby Mathew748be1d2016-05-05 14:10:46 +0100153 * The following function initializes the cpu_context for a CPU specified by
154 * its `cpu_idx` for first use, and sets the initial entrypoint state as
155 * specified by the entry_point_info structure.
156 ******************************************************************************/
157void cm_init_context_by_index(unsigned int cpu_idx,
158 const entry_point_info_t *ep)
159{
160 cpu_context_t *ctx;
161 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100162 cm_setup_context(ctx, ep);
Soby Mathew748be1d2016-05-05 14:10:46 +0100163}
164
165/*******************************************************************************
166 * The following function initializes the cpu_context for the current CPU
167 * for first use, and sets the initial entrypoint state as specified by the
168 * entry_point_info structure.
169 ******************************************************************************/
170void cm_init_my_context(const entry_point_info_t *ep)
171{
172 cpu_context_t *ctx;
173 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100174 cm_setup_context(ctx, ep);
Soby Mathew748be1d2016-05-05 14:10:46 +0100175}
176
177/*******************************************************************************
178 * Prepare the CPU system registers for first entry into secure or normal world
179 *
180 * If execution is requested to hyp mode, HSCTLR is initialized
181 * If execution is requested to non-secure PL1, and the CPU supports
182 * HYP mode then HYP mode is disabled by configuring all necessary HYP mode
183 * registers.
184 ******************************************************************************/
185void cm_prepare_el3_exit(uint32_t security_state)
186{
David Cunadofee86532017-04-13 22:38:29 +0100187 uint32_t hsctlr, scr;
Soby Mathew748be1d2016-05-05 14:10:46 +0100188 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100189 bool el2_unused = false;
Soby Mathew748be1d2016-05-05 14:10:46 +0100190
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000191 assert(ctx != NULL);
Soby Mathew748be1d2016-05-05 14:10:46 +0100192
193 if (security_state == NON_SECURE) {
194 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000195 if ((scr & SCR_HCE_BIT) != 0U) {
Soby Mathew748be1d2016-05-05 14:10:46 +0100196 /* Use SCTLR value to initialize HSCTLR */
David Cunadofee86532017-04-13 22:38:29 +0100197 hsctlr = read_ctx_reg(get_regs_ctx(ctx),
Soby Mathew748be1d2016-05-05 14:10:46 +0100198 CTX_NS_SCTLR);
David Cunadofee86532017-04-13 22:38:29 +0100199 hsctlr |= HSCTLR_RES1;
Soby Mathew748be1d2016-05-05 14:10:46 +0100200 /* Temporarily set the NS bit to access HSCTLR */
201 write_scr(read_scr() | SCR_NS_BIT);
202 /*
203 * Make sure the write to SCR is complete so that
204 * we can access HSCTLR
205 */
206 isb();
David Cunadofee86532017-04-13 22:38:29 +0100207 write_hsctlr(hsctlr);
Soby Mathew748be1d2016-05-05 14:10:46 +0100208 isb();
209
210 write_scr(read_scr() & ~SCR_NS_BIT);
211 isb();
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000212 } else if ((read_id_pfr1() &
213 (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) {
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100214 el2_unused = true;
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000215
David Cunado5f55e282016-10-31 17:37:34 +0000216 /*
217 * Set the NS bit to access NS copies of certain banked
218 * registers
219 */
Soby Mathew748be1d2016-05-05 14:10:46 +0100220 write_scr(read_scr() | SCR_NS_BIT);
221 isb();
222
David Cunadofee86532017-04-13 22:38:29 +0100223 /*
224 * Hyp / PL2 present but unused, need to disable safely.
225 * HSCTLR can be ignored in this case.
226 *
227 * Set HCR to its architectural reset value so that
228 * Non-secure operations do not trap to Hyp mode.
229 */
230 write_hcr(HCR_RESET_VAL);
Soby Mathew748be1d2016-05-05 14:10:46 +0100231
David Cunadofee86532017-04-13 22:38:29 +0100232 /*
233 * Set HCPTR to its architectural reset value so that
234 * Non-secure access from EL1 or EL0 to trace and to
235 * Advanced SIMD and floating point functionality does
236 * not trap to Hyp mode.
237 */
238 write_hcptr(HCPTR_RESET_VAL);
Soby Mathew748be1d2016-05-05 14:10:46 +0100239
David Cunadofee86532017-04-13 22:38:29 +0100240 /*
241 * Initialise CNTHCTL. All fields are architecturally
242 * UNKNOWN on reset and are set to zero except for
243 * field(s) listed below.
244 *
245 * CNTHCTL.PL1PCEN: Disable traps to Hyp mode of
246 * Non-secure EL0 and EL1 accessed to the physical
247 * timer registers.
248 *
249 * CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of
250 * Non-secure EL0 and EL1 accessed to the physical
251 * counter registers.
252 */
253 write_cnthctl(CNTHCTL_RESET_VAL |
254 PL1PCEN_BIT | PL1PCTEN_BIT);
Soby Mathew748be1d2016-05-05 14:10:46 +0100255
David Cunadofee86532017-04-13 22:38:29 +0100256 /*
257 * Initialise CNTVOFF to zero as it resets to an
258 * IMPLEMENTATION DEFINED value.
259 */
Soby Mathew748be1d2016-05-05 14:10:46 +0100260 write64_cntvoff(0);
261
David Cunadofee86532017-04-13 22:38:29 +0100262 /*
263 * Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR
264 * respectively.
265 */
Soby Mathew748be1d2016-05-05 14:10:46 +0100266 write_vpidr(read_midr());
267 write_vmpidr(read_mpidr());
268
269 /*
David Cunadofee86532017-04-13 22:38:29 +0100270 * Initialise VTTBR, setting all fields rather than
271 * relying on the hw. Some fields are architecturally
272 * UNKNOWN at reset.
273 *
274 * VTTBR.VMID: Set to zero which is the architecturally
275 * defined reset value. Even though EL1&0 stage 2
276 * address translation is disabled, cache maintenance
277 * operations depend on the VMID.
278 *
279 * VTTBR.BADDR: Set to zero as EL1&0 stage 2 address
280 * translation is disabled.
Soby Mathew748be1d2016-05-05 14:10:46 +0100281 */
David Cunadofee86532017-04-13 22:38:29 +0100282 write64_vttbr(VTTBR_RESET_VAL &
283 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
284 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
David Cunado5f55e282016-10-31 17:37:34 +0000285
286 /*
David Cunadofee86532017-04-13 22:38:29 +0100287 * Initialise HDCR, setting all the fields rather than
288 * relying on hw.
289 *
290 * HDCR.HPMN: Set to value of PMCR.N which is the
291 * architecturally-defined reset value.
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100292 *
293 * HDCR.HLP: Set to one so that event counter
294 * overflow, that is recorded in PMOVSCLR[0-30],
295 * occurs on the increment that changes
296 * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is
297 * implemented. This bit is RES0 in versions of the
298 * architecture earlier than ARMv8.5, setting it to 1
299 * doesn't have any effect on them.
300 * This bit is Reserved, UNK/SBZP in ARMv7.
301 *
302 * HDCR.HPME: Set to zero to disable EL2 Event
303 * counters.
David Cunado5f55e282016-10-31 17:37:34 +0000304 */
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100305#if (ARM_ARCH_MAJOR > 7)
306 write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT |
307 ((read_pmcr() & PMCR_N_BITS) >>
308 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
309#else
310 write_hdcr((HDCR_RESET_VAL |
311 ((read_pmcr() & PMCR_N_BITS) >>
312 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
313#endif
David Cunadoc14b08e2016-11-25 00:21:59 +0000314 /*
David Cunadofee86532017-04-13 22:38:29 +0100315 * Set HSTR to its architectural reset value so that
316 * access to system registers in the cproc=1111
317 * encoding space do not trap to Hyp mode.
318 */
319 write_hstr(HSTR_RESET_VAL);
320 /*
321 * Set CNTHP_CTL to its architectural reset value to
322 * disable the EL2 physical timer and prevent timer
323 * interrupts. Some fields are architecturally UNKNOWN
324 * on reset and are set to zero.
David Cunadoc14b08e2016-11-25 00:21:59 +0000325 */
David Cunadofee86532017-04-13 22:38:29 +0100326 write_cnthp_ctl(CNTHP_CTL_RESET_VAL);
Soby Mathew748be1d2016-05-05 14:10:46 +0100327 isb();
328
329 write_scr(read_scr() & ~SCR_NS_BIT);
330 isb();
331 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000332 enable_extensions_nonsecure(el2_unused);
Soby Mathew748be1d2016-05-05 14:10:46 +0100333 }
334}