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git01.mediatek.com / filogic / atf / 3aebacfea85b54309c261de703f0778abdcbc579 / . / plat / xilinx / zynqmp / platform.mk
blob: a31e31d058b4adedfa6a816c9ab8cf888b257926 [file] [log] [blame]
Antonio Nino Diaz493bf332016-12-14 14:31:32 +0000[diff] [blame]1#
dp-arm230011c2017-03-07 11:02:47 +0000[diff] [blame]2# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]3#
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4# SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]5
Soren Brinkmannba8309d2017-04-06 11:44:27 -0700[diff] [blame]6override ERRATA_A53_855873 := 1
Masahiro Yamada8cf895c2016-12-19 17:41:47 +0900[diff] [blame]7override ENABLE_PLAT_COMPAT := 0
8override PROGRAMMABLE_RESET_ADDRESS := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]9PSCI_EXTENDED_STATE_ID := 1
10A53_DISABLE_NON_TEMPORAL_HINT := 0
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700[diff] [blame]11SEPARATE_CODE_AND_RODATA := 1
Masahiro Yamada8cf895c2016-12-19 17:41:47 +0900[diff] [blame]12override RESET_TO_BL31 := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]13
David Cunadoc5b0c0f2017-10-31 23:19:21 +0000[diff] [blame]14# Do not enable SVE
15ENABLE_SVE_FOR_NS := 0
16
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]17ifdef ZYNQMP_ATF_MEM_BASE
18 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
19
20 ifndef ZYNQMP_ATF_MEM_SIZE
21 $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
22 endif
23 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]24
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]25 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
26 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
27 endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]28endif
29
Soren Brinkmann4a9ca042016-04-14 10:27:00 -0700[diff] [blame]30ifdef ZYNQMP_BL32_MEM_BASE
31 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
32
33 ifndef ZYNQMP_BL32_MEM_SIZE
34 $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
35 endif
36 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
37endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]38
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -0700[diff] [blame]39ZYNQMP_CONSOLE ?= cadence
40$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
41
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]42PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
43 -Iinclude/plat/arm/common/aarch64/ \
44 -Iplat/xilinx/zynqmp/include/ \
45 -Iplat/xilinx/zynqmp/pm_service/
46
Soby Mathewcc037c12016-04-08 16:42:58 +0100[diff] [blame]47PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
48 lib/xlat_tables/aarch64/xlat_tables.c \
Soren Brinkmanne5bdcaa2016-06-22 09:02:56 -0700[diff] [blame]49 drivers/delay_timer/delay_timer.c \
50 drivers/delay_timer/generic_delay_timer.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]51 drivers/arm/gic/common/gic_common.c \
52 drivers/arm/gic/v2/gicv2_main.c \
53 drivers/arm/gic/v2/gicv2_helpers.c \
Soby Mathew17231132016-08-08 12:33:06 +0100[diff] [blame]54 drivers/cadence/uart/aarch64/cdns_console.S \
55 drivers/console/aarch64/console.S \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]56 plat/arm/common/aarch64/arm_helpers.S \
57 plat/arm/common/arm_cci.c \
Soby Mathew0eb965b2016-07-07 08:45:56 +0100[diff] [blame]58 plat/arm/common/arm_common.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]59 plat/arm/common/arm_gicv2.c \
60 plat/common/plat_gicv2.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]61 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
62 plat/xilinx/zynqmp/aarch64/zynqmp_common.c
63
64BL31_SOURCES += drivers/arm/cci/cci.c \
65 lib/cpus/aarch64/aem_generic.S \
66 lib/cpus/aarch64/cortex_a53.S \
Soby Mathewf6c41082016-05-03 12:31:18 +0100[diff] [blame]67 plat/common/plat_psci_common.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]68 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
69 plat/xilinx/zynqmp/plat_psci.c \
70 plat/xilinx/zynqmp/plat_zynqmp.c \
Michal Simekef8f5592015-06-15 14:22:50 +0200[diff] [blame]71 plat/xilinx/zynqmp/plat_startup.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]72 plat/xilinx/zynqmp/plat_topology.c \
73 plat/xilinx/zynqmp/sip_svc_setup.c \
Wendy Liang3aebacf2017-09-13 11:02:42 -0700[diff] [blame^]74 plat/xilinx/zynqmp/zynqmp_ipi.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800[diff] [blame]75 plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
76 plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
77 plat/xilinx/zynqmp/pm_service/pm_ipi.c \
78 plat/xilinx/zynqmp/pm_service/pm_client.c